has two main interfaces: the control interface and the digital audio interface.
The control interface is controlled via an I2C bus. Here, some of the config-uration parameters are defined, such as the input and output selections (line in, microphone in, line out, headphone out), the audio resolution, the sampling rate, the output volume, and so on. This configuration is always done in the setup of each audio program. For this project, the 48kHz16-bit option has been chosen, which is a standard audio quality. However, the actual sampling rate is not exactly 48, but 52.083 kHz. This is because the WM8731 requires a source clock signal of 12.288 M Hz to sample audio at 48 kHz. Instead, the provided clock is 13.33 M Hz, which is the Patmos frequency of 80 M Hz divided by 6.
So the sampling rate is 48·13.3312.288 = 52.083 kHz. This does not represent any decrease in the performance or in the audio quality of the system because the sampling rate is even greater than 48 kHz, so the Nyquist theorem is fulfilled.
The digital audio interface is used for the input and output of the digital audio samples. This is done through 5 wires: DACDAT, DACLRC, ADCDAT, ADCLRC andBCLK. TheLRCsignals are used for sampling synchronization: they provide a pulse every sampling period. TheDATsignals transfer the actual audio data, bit by bit. Finally, theBCLKsignal is a synchronization clock for every sample bit.
The WM8731 supports many digital audio interfacing modes, and here the cho-sen one is the DSP mode A. Briefly, this means that a LRCpulse comes every 256 BCLK cycles. After each pulse, first the 16 bits of the left channel sample are transferred on everyBCLK pulse, and then the 16-bits of the right channel.
After that, there is no data for the next 223 cycles, until the next LRC pulse happens.
Both I2C signals and all the mentioned digital audio interfacing signals are connected from the Altera DE2-115 FPGA to the WM8731 in the board. The FPGA is intended to be used as a master, and the WM8731 is the slave.
4.2 Design of the Audio Interface 43
The Audio Interface and its internal components are shown in Figure 4.1. The HDL implementation of the input and output buffers can be found in appendix A, which are the main contribution to the interface done in this project. The rest of the components can be found at the Patmos GitHub repository1. Each component does the following:
• AudioInterface: it is the top component, which connects the sub-compo-nents between them, to Patmos via OCP or to the WM8731 audio CODEC through the FPGA ports.
• AudioClkGen: it generates the 13.33 M Hz XCLK and BCLK signals from the 80 M Hzclock of Patmos.
• AudioI2C: when Patmos writes new data in the configuration data and address registers, this block transfers it to the WM8731 in the I2C format.
It then waits for the acknowledge from the CODEC.
• AudioADCandAudioDAC: these two blocks exchange the input and output audio data respectively between Patmos and the audio CODEC, using the explained DSP mode A format. The AudioADCgenerates theADCLRC pulse, and stores the data from ADCDAT in the left and right input audio registers connected to the input buffer. The AudioDAC block does the inverse process for the output.
• AudioADCBuffer and AudioDACBuffer: these are the input and output buffers respectively. They exchange data with Patmos via handshaking, and are essential to implement the flow control communication used in the system, explained in Subsection 5.1.1. However, the latency of the system is also increased by increasing the buffer sizes, and one must be careful with this so that the real-time perception of audio is not lost.
As mentioned before, the buffers are the main contribution to the interface done in this project (apart from minor changes in other components, to adapt to the buffers). Their hardware implementation is shown in appendix Sections A.1 and A.2. Some of the main characteristics of them are explained in the following points:
• Both the AudioDACBuffer and the AudioADCBufferare implemented as circular FIFO buffers which wrap around, as explained in [10, Chapter 28].
For this, the buffer size must always be a power of 2, where the maximum size is 256 (this value could easily be increased in a bigger platform).
1https://github.com/t-crest/patmos/tree/master/hardware/src/io
AudioADCBuffer
AudioDACBuffer AudioClkGen
audioAdcEnReg
audioDacEnReg audioAdcLRegaudioAdcRRegaudioAdcBufferReadPulseRegaudioAdcBufferSizeRegaudioAdcBufferEmptyReg
audioDacLRegaudioDacRRegaudioDacBufferWritePulseRegaudioDacBufferSizeRegaudioDacBufferFullReg Audio Interface
AudioI2C i2cDataRegi2cAddrRegi2cReqRegi2cAckReg AudioADCAudioDAC XCLKBCLK xclkbclk
audioLAdcaudioRAdcenAdcreadEnAdc
audioLDacaudioRDacenDacwriteEnAdcconvEndAdc ADCLRCADCDATDACLRCDACDAT
sdOutsdInsClkwe I2Cout SCLKSDIN PATMOSWM8731
Figure4.1:Architecturaloverviewoftheaudiointerface,showingitscomponentsandconnectionstoPatmos(viaOCP)andtotheWM8731audioCODEC.ThecoloredbackgroundindicatesthatthecomponentsareonthesameFPGAchip.
4.2 Design of the Audio Interface 45
• They have read and write pointers, whose bitlength is equal to the amount of bits needed to represent the buffer length, for easy wrapping around (for instance, 8-bit pointers for a 256-sample buffer). The pointers are automatically incremented when a read or write is issued by Patmos or by theAudioADC/AudioDACblocks.
• A state machine takes care of the state of the buffer, with states forempty, almost-empty, idle, almost-full andfull situations. The state is idle when the buffer is not empty, almost empty, full or almost full. Thealmostcases are needed for when the buffer size is 2 samples, because a transition from idle to empty or to full cannot be distinguished without these states.
• The state machines also generate empty and full flags. Patmos can read audio data while the input buffer is not empty, and it can output data while the output buffer is not full. If the output buffer is empty during a time range longer than the sampling period, undesired interruptions will be heard in the processed audio output because some samples have been dropped out.
• Finally, the state machine of the AudioDACBuffer also drives the enable signal of theAudioDACblock. The audio output is enabled only when the DAC buffer is not empty (i.e. there is data to output). The AudioADC enable signal is always high, and if the input buffer is full, input data is overwritten in the buffer.
An important design decision has been to make the read/write pointers auto-incrementing. This means that Patmos can read an input sample only once. If a specific audio effect needs to buffer a group of samples, they need to be stored somewhere else when reading. This is exactly what happens on the filter effects, where a buffer is needed to store the newest input samples. These samples are stored in the SPM because it is a fast access memory. This is represented in Figure 4.2, showing that the samples for filter calculation are stored in the SPM.
write_pointer
read_pointer ADC Buffer
I/O PATMOS DSPM
Figure 4.2: Representation of the input buffer and Patmos, showing how the latest samples needed for filter calculation are transferred to the data SPM.
Another possibility would have been to be able to change the read pointer of the buffer from Patmos, so that storing the input samples in the SPM would not be needed. But this requires a more complex buffer (it would not be a FIFO anymore) which is not needed for this project, as the data SPM is enough to store the buffers of each effect.