9.3 Future Work
9.3.3 Handshake Level Model
With the large increase in simulation speed observed by going to a high-level model, it could be interesting to see how a handshake level model performs. It is easier to achieve a timing accurate model using handshake level modeling, due to the finer granularity of the model. Where the link component in the high-level model cov-ers all forward latencies, they would be distributed between smaller components in a handshake level model. Power consumption would also be estimated more accu-rately, due to the finer granularity.
In a model at the handshake level, it would also be easier to replace model com-ponents with actual implementations than in a high-level model, as there is no need for a conversion between handshakes and the model. However, investigating high-level concepts such as adaptive routing schemes or system design elements such as the number of links into and out of a node would be more difficult in a handshake
70 CHAPTER 9 DISCUSSION
level model, as components would have to be added and connected by signals to other components. In the current high-level model, adding a port to a node can be done simply by increasing the size of the arrays that represent the sc_ports and the routing tables.
The two different models each have advantages and disadvantages, and the better choice might actually be not to have one or the other, but both. Early system-level exploration would then use the high-level model to investigate topologies, application mappings and GS connection routings, while the handshake level model could be applied to provide a more fine-grained picture of timing and power consumption.
Network developers would use the handshake level model to investigate the impact of new implementations of components.
Chapter 10
Conclusions
In this work, the design, implementation and testing of a high-level model of MANGO has been presented. The purpose of the model was to obtain a high simulation speed while being accurate in terms of timing. A model that meets both requirements has been designed, and implemented, but some issues are present in the implementation that should be corrected.
A small test system has been setup in order to compare simulations of the actual implementation of MANGO and the model. The two behave comparably when iso-lated flits are transmitted through the network, as happens in single flit transactions.
When multiple flits are present on a GS connection however, they interact differently in the model than in MANGO. This may be caused by the fact that the values used for delays in the model are only estimated and not based on measurements in simulations of the current implementation of MANGO.
The test system demonstrates using actual implementations of components in conjunction with the model. The actual implementations of the network adapters are used, and a conversion module has been implemented that converts between hand-shakes and the model. This module shows the general approach to and feasibility of replacing components from the model with those from the actual implementation.
The performance profiler available in ModelSim has been used to measure the execution time of various parts of the test system in simulations of both MANGO and the model. A drop in the simulation time was observed when replacing MANGO with the model. However, the network adapters used in both simulations are the ones from MANGO, which are implemented as netlists of standard cells, which means the drop in total simulation time is relatively modest. However, in the simulation of the model, the majority of the execution time spent in user code was spent in the NAs.
The speedup observed in the network between the simulation of MANGO and the model indicates that the magnitude of the achievable speedup by using a high-level model is roughly a factor 1000.
71
Bibliography
[1] T. Bjerregaard. Programming and using connections in the mango network-on-chip. To be submitted.
[2] T. Bjerregaard. The MANGO clockless network-on-chip: Concepts and im-plementation. PhD thesis, Informatics and Mathematical Modelling, Technical University of Denmark, DTU, Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby, 2005.
[3] T. Bjerregaard, S. Mahadevan, and J. Sparsø. A channel library for asynchronous circuit design supporting mixed-mode modelling. In Odysseas Koufopavlou Enrico Macii, Vassilis Paliouras, editor,PATMOS 2004 (14th Intl. Workshop on Power and Timing Modeling, Optimization and Sim-ulation), Lecture Notes in Computer Science, LNCS3254, pages 301–310.
Springer, 2004.
[4] T. Bjerregaard and J. Sparsø. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In Proceed-ings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05), pages 1226–1231. IEEE Computer Society, mar 2005.
[5] T. Bjerregaard and J. Sparsø. A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. InProceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’05), pages 34–43. IEEE Computer Society, mar 2005.
[6] T. Bjerregaard and J. Sparsø. Implementation of guaranteed services in the MANGO clockless network-on-chip.IEE Proceedings: Computing and Digital Techniques, 2006. Accepted for publication.
[7] Tobias Bjerregaard and Shankar Mahadevan. A survey of research and practices of network-on-chip.ACM Computing Surveys, TBA. Accepted.
[8] David Culler, J. P. Singh, and Anoop Gupta.Parallel Computer Architecture, A Hardware/Software Approach. Morgan Kaufmann, 1999.
[9] Thorsten Grötker, Stan Liao, Grant Martin, and Stuart Swan. System Design with SystemC. Kluwer Academic Publishers, 2002.
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[10] http://www.imm.dtu.dk/arts.
[11] J. Madsen, S. Mahadevan, K. Virk, and M. J. Gonzalez. Network-on-chip mod-eling for system-level multiprocessor simulation. In The 24th IEEE Interna-tional Real-Time Systems Symposium, pages 265–274. IEEE Computer Society, dec 2003.
[12] S. Mahadevan, M. Storgaard, J. Madsen, and K. M. Virk. ARTS: A system-level framework for modeling mpsoc components and analysis of their causality. In 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer So-ciety, sep 2005.
[13] http://www.model.com.
[14] http://www.ocpip.org.
[15] J. Sparsø. Asynchronous circuit design - a tutorial. InChapters 1-8 in ”Prin-ciples of asynchronous circuit design - A systems Perspective”, pages 1–152.
Kluwer Academic Publishers, Boston/Dordrecht/London, dec 2001.
A ppendix A Sour ce Code Thisappendixliststhesourcecodeofthesourcefilesproduced inthiswork.Ashortdescriptiontothefilewillbegivenwhere necessary. A.1 T op Le v el Files
A.1.1interfaces.h 1/∗ 2Componentinterfaces.Allcomponentsmustinheritfromthese. 3∗/ 4 5#ifndef_INTERFACES_H 6#define_INTERFACES_H 7 8#include<systemc> 9#include"types.h" 10
11/∗Arbiter∗/ 12classarbiter_if:virtualpublicsc_core::sc_interface{ 13 14public: 15virtualvoidarbitrate(flit∗,int)=0; 16 17}; 18 19/∗VirtualChannel∗/ 20classvc_transmitter_if:virtualpublicsc_core::sc_interface{ 21 22public: 23virtualvoidsend(flit∗)=0; 24 25}; 26 27classvc_receiver_if:virtualpublicsc_core::sc_interface{ 28 29public: 30virtualvoidunlock()=0; 31virtualvoidarb_ready(){} 32 33}; 34 35/∗Link∗/ 36classlink_transmitter_if:virtualpublicsc_core::sc_interface{ 37 38public: 39virtualvoidsend(flit∗)=0; 40 41}; 42 43classlink_receiver_if:virtualpublicsc_core::sc_interface{ 44 45public: 46virtualvoidunlock_gs(int)=0; 47virtualvoidcredit_be(int)=0; 48 49}; 50 51/∗Node∗/ 52classnode_transmitter_if:virtualpublicsc_core::sc_interface{ 53 54public: 55/∗Unlocksfromlinks∗/
A.1
A.2 APPENDIX A SOURCE CODE
56virtualvoidunlock_gs(constint,constdirection)=0; 57virtualvoidcredit_be(constint,constdirection)=0; 58 59}; 60 61classnode_receiver_if:virtualpublicsc_core::sc_interface{ 62 63public: 64virtualvoidsend(flit∗)=0; 65 66}; 67 68classnode_arbiter_if:virtualpublicsc_core::sc_interface{ 69 70public: 71virtualvoidarb_send(flit∗,constdirection)=0; 72virtualvoidarb_ready(constint,constdirection)=0; 73 74}; 75 76classnode_internal_if:virtualpublicsc_core::sc_interface{ 77 78public: 79/∗UnlocksfromVCs∗/ 80virtualvoidunlock(constint,constdirection)=0; 81virtualvoidcredit(constint,constdirection)=0; 82 83}; 84 85classnode_na_receiver_if:virtualpublicsc_core::sc_interface{ 86 87public: 88virtualvoidna_send(flit∗)=0; 89 90}; 91 92classnode_na_transmitter_if:virtualpublicsc_core::sc_interface { 93 94public: 95virtualvoidna_unlock_gs(constint)=0; 96 97}; 98 99/∗NetworkAdapter∗/
100classna_if:virtualpublicsc_core::sc_interface{ 101 102public: 103virtualvoidunlock(constint)=0; 104virtualvoidsend(flit∗)=0; 105 106}; 107 108#endif A.1.2types.h 1/∗ 2TypesforuseinNoCmodel. 3 4Contains: 5Direction 6Flit 7 8∗/ 9 10#ifndef_TYPES_H 11#define_TYPES_H 12 13#include<vector> 14 15/∗Thenon−localdirectionsmustbenumberedfrom0ton−1∗/ 16typedefintdirection; 17constdirectiondir_north=0; 18constdirectiondir_east=1; 19constdirectiondir_south=2; 20constdirectiondir_west=3; 21constdirectiondir_local=4; 22constdirectiondir_invalid=−1; 23 24/∗Enumtoidentifythetypeofflit∗/ 25enumflittype{ft_invalid,ft_data}; 26 27/∗Non−instantiableflitclass.Allflitsinheritfromthis∗/ 28classflit{ 29 30public: 31constflittypeget_type()const{ 32return_type;
COMPONENTS A.3
33} 34 35constboolis_last()const{ 36return_last; 37} 38 39constdirectionget_direction()const{ 40return_dir; 41} 42 43constintget_vc()const{ 44return_vc; 45} 46 47voidset_direction(directiond){ 48_dir=d; 49} 50 51voidset_vc(intvc){ 52_vc=vc; 53} 54 55protected: 56flit(constflittypeft,constboollast):_type(ft),_last(last) { 57 58} 59 60private: 61constflittype_type; 62constbool_last; 63int_vc; 64direction_dir; 65 66}; 67 68/∗Templateddataflit∗/ 69template<typenameT> 70classflit_data:publicflit{ 71 72public: 73Tget_data(){ 74return_data; 75} 76 77flit_data(constTdata,constboollast):flit(ft_data,last), _data(data){ 78 79} 80 81private: 82T_data; 83 84}; 85 86#endif
A.2 Components
A.2.1arbiter.h 1/∗ 2HeaderforthemodeloftheALGarbiter 3∗/ 4 5#ifndef_ARBITER_H 6#define_ARBITER_H 7 8#include<systemc> 9#include"../interfaces.h" 10#include"../types.h" 11 12/∗Numberofinputs∗/ 13constunsignedintN=8; 14 15classarbiter:publicsc_core::sc_module,publicarbiter_if{ 16 17public: 18/∗Ports∗/ 19sc_core::sc_port<node_arbiter_if>nde; 20 21/∗Inherited(virtual)functions∗/ 22voidarbitrate(flit∗,int); 23 24SC_HAS_PROCESS(arbiter); 25 26arbiter(sc_core::sc_module_namen,constsc_core::sc_time&lct, constdirectiondir);A.4 APPENDIX A SOURCE CODE
27 28private: 29voiddo_arbitrate(); 30booltransmit(); 31 32constsc_core::sc_time_link_cycle_time; 33 34/∗Admissioncontrolandstaticpriorityqueue∗/ 35flit∗_hold_q[N]; 36flit∗_spq[N]; 37bool_hold_q_valid[N]; 38bool_spq_valid[N]; 39 40/∗Busyindication,waitsignalsforadmissioncontrolandtime outevent∗/ 41bool_busy; 42bool_wait[N][N]; 43sc_core::sc_event_time_out; 44 45constdirection_dir; 46 47}; 48 49#endif A.2.2arbiter.cpp 1/∗ 2ArbiterimplementingALG 3∗/ 4 5#include"arbiter.h" 6 7voidarbiter::arbitrate(flit∗f,intvc){ 8_hold_q[vc]=f; 9_hold_q_valid[vc]=true; 10if(!_busy){ 11do_arbitrate(); 12} 13} 14 15voidarbiter::do_arbitrate(){ 16boolvc_wait=true; 17boolgraduated=false;
18 19/∗Attempttransmit∗/ 20booltx=transmit(); 21 22/∗Graduatefromholdqueuetospq∗/ 23for(inti=0;i<N;++i){ 24if(_hold_q_valid[i]){ 25if(i<7){ 26vc_wait=true; 27}else{ 28vc_wait=false; 29} 30for(intj=i+1;j<N;++j){ 31vc_wait=vc_wait&_wait[i][j]; 32} 33if(!vc_wait){ 34_spq[i]=_hold_q[i]; 35_spq_valid[i]=true; 36_hold_q_valid[i]=false; 37/∗Arbiterreadyfornewinput∗/ 38nde−>arb_ready(i,_dir); 39} 40graduated=true; 41} 42} 43 44/∗Transmithighestpriorityinspq,iffirsttransmitfailed∗/ 45if(!tx&&graduated){ 46transmit(); 47} 48} 49 50boolarbiter::transmit(){ 51for(inti=0;i<N;++i){ 52if(_spq_valid[i]){ 53_spq_valid[i]=false; 54nde−>arb_send(_spq[i],_dir); 55_busy=true; 56_time_out.notify(_link_cycle_time); 57 58/∗VCimustnowwaitforvalidlowerprioritiesinspq∗/ 59for(intj=i+1;j<N;++j){ 60_wait[i][j]=_spq_valid[j]; 61} 62
COMPONENTS A.5
63/∗VCs0..i−1mustnolongerwaitforVCi∗/ 64for(intj=0;j<i;++j){ 65_wait[j][i]=false; 66} 67 68/∗Aflitwastransmitted∗/ 69returntrue; 70} 71} 72/∗Noflittransmitted∗/ 73_busy=false; 74returnfalse; 75} 76 77arbiter::arbiter(sc_core::sc_module_namen,constsc_core::sc_time& lct,constdirectiondir):sc_core::sc_module(n), _link_cycle_time(sc_core::sc_time(5,sc_core::SC_NS)),_dir( dir){ 78_busy=false; 79for(inti=0;i<N;++i){ 80_hold_q_valid[i]=false; 81_spq_valid[i]=false; 82for(intj=0;j<N;++j){ 83_wait[i][j]=false; 84} 85} 86SC_METHOD(do_arbitrate); 87sensitive<<_time_out; 88dont_initialize(); 89} A.2.3link.h 1/∗ 2Alink,implementedasastd::queuewithconstantdelays 3∗/ 4 5#ifndef_LINK_H 6#define_LINK_H 7 8#include<systemc> 9#include<queue> 10#include"../types.h" 11#include"../interfaces.h"
12 13classmango_link:publiclink_transmitter_if,public link_receiver_if,publicsc_core::sc_module{ 14 15public: 16/∗Ports∗/ 17sc_core::sc_port<node_transmitter_if>transmitter; 18sc_core::sc_port<node_receiver_if>receiver; 19 20/∗Inherited(virtual)functions∗/ 21voidunlock_gs(inti); 22voidcredit_be(inti); 23voidsend(flit∗f); 24 25SC_HAS_PROCESS(mango_link); 26 27/∗Constructor∗/ 28mango_link(sc_core::sc_module_namen,constdirectiondir,const sc_core::sc_time&send_delay,constsc_core::sc_time& unlock_gs_delay,constsc_core::sc_time&credit_be_delay); 29 30private: 31/∗Time−outfunctions∗/ 32voiddo_unlock_gs(); 33voiddo_credit_be(); 34voiddo_send(); 35 36/∗Directionoflink∗/ 37constdirection_dir; 38 39/∗Delays∗/ 40constsc_core::sc_time&_send_delay; 41constsc_core::sc_time&_unlock_gs_delay; 42constsc_core::sc_time&_credit_be_delay; 43 44/∗Queues∗/ 45std::queue<std::pair<flit∗,sc_core::sc_time>>_send_fifo; 46std::queue<std::pair<int,sc_core::sc_time>>_unlock_gs_fifo; 47std::queue<std::pair<int,sc_core::sc_time>>_credit_be_fifo; 48 49/∗Time−outevents∗/ 50sc_core::sc_event_e_send; 51sc_core::sc_event_e_unlock_gs; 52sc_core::sc_event_e_credit_be; 53
A.6 APPENDIX A SOURCE CODE
54}; 55 56#endif A.2.4link.cpp 1/∗ 2Alinkwithconstantdelays 3∗/ 4 5#include"link.h" 6 7voidmango_link::unlock_gs(inti){ 8_unlock_gs_fifo.push(std::make_pair<int,sc_core::sc_time>(i, simcontext()−>time_stamp()+_unlock_gs_delay)); 9if(_unlock_gs_fifo.size()==1){ 10_e_unlock_gs.notify(_unlock_gs_delay); 11} 12} 13 14voidmango_link::credit_be(inti){ 15_credit_be_fifo.push(std::make_pair<int,sc_core::sc_time>(i, simcontext()−>time_stamp()+_credit_be_delay)); 16if(_credit_be_fifo.size()==1){ 17_e_credit_be.notify(_credit_be_delay); 18} 19} 20 21voidmango_link::send(flit∗f){ 22_send_fifo.push(std::make_pair<flit∗,sc_core::sc_time>(f, simcontext()−>time_stamp()+_send_delay)); 23if(_send_fifo.size()==1){ 24_e_send.notify(_send_delay); 25} 26} 27 28/∗Activatedwhenunlockarrives∗/ 29voidmango_link::do_unlock_gs(){ 30transmitter−>unlock_gs(_unlock_gs_fifo.front().first,_dir); 31_unlock_gs_fifo.pop(); 32if(_unlock_gs_fifo.size()>0){ 33_e_unlock_gs.notify(_unlock_gs_fifo.front().second−simcontext ()−>time_stamp()); 34}
35} 36 37/∗Activatedwhencreditarrives∗/ 38voidmango_link::do_credit_be(){ 39transmitter−>credit_be(_credit_be_fifo.front().first,_dir); 40_credit_be_fifo.pop(); 41if(_credit_be_fifo.size()>0){ 42_e_credit_be.notify(_credit_be_fifo.front().second−simcontext ()−>time_stamp()); 43} 44} 45 46/∗Activatedwhenflitarrives∗/ 47voidmango_link::do_send(){ 48receiver−>send(_send_fifo.front().first); 49_send_fifo.pop(); 50if(_send_fifo.size()>0){ 51_e_send.notify(_send_fifo.front().second−simcontext()−> time_stamp()); 52} 53} 54 55mango_link::mango_link(sc_core::sc_module_namen,constdirection dir,constsc_core::sc_time&send_delay,constsc_core:: sc_time&unlock_gs_delay,constsc_core::sc_time& credit_be_delay):sc_core::sc_module(n),_dir(dir), _send_delay(send_delay),_unlock_gs_delay(unlock_gs_delay), _credit_be_delay(credit_be_delay){ 56SC_METHOD(do_send); 57dont_initialize(); 58sensitive<<_e_send; 59SC_METHOD(do_unlock_gs); 60dont_initialize(); 61sensitive<<_e_unlock_gs; 62SC_METHOD(do_credit_be); 63dont_initialize(); 64sensitive<<_e_credit_be; 65} A.2.5vc.h 1/∗ 2Virtualchannels 3∗/
COMPONENTS A.7
4 5#ifndef_VC_H 6#define_VC_H 7 8#include<systemc> 9#include<queue> 10 11#include"../interfaces.h" 12#include"../types.h" 13 14/∗GeneralVC,nottobeinstantiated∗/ 15classvc:publicsc_core::sc_module,publicvc_transmitter_if, publicvc_receiver_if{ 16 17public: 18vc(sc_core::sc_module_name); 19 20}; 21 22/∗GuaranteedServiceVC∗/ 23classgs_vc:publicvc{ 24 25public: 26sc_core::sc_port<arbiter_if>arb; 27sc_core::sc_port<node_internal_if>nde; 28 29/∗Inheritedfunctions∗/ 30voidsend(flit∗); 31voidunlock(); 32 33/∗Constructor∗/ 34gs_vc(sc_core::sc_module_name,constintid,constdirectiondir) ; 35 36private: 37/∗IDanddirection∗/ 38constint_id; 39constdirection_dir; 40 41/∗Latchesandindicationsofvalidity∗/ 42flit∗_lock_box; 43bool_lock_box_valid; 44 45flit∗_unlock_box; 46bool_unlock_box_valid;
47 48flit∗_buffer; 49bool_buffer_valid; 50 51}; 52 53#endif A.2.6vc.cpp 1#include"vc.h" 2 3/∗ 4Generalabstract/virtualVCbufffer 5∗/ 6 7vc::vc(sc_core::sc_module_namen):sc_core::sc_module(n){ 8 9} 10 11/∗ 12GuarateedServiceVCBuffer 13∗/ 14 15voidgs_vc::send(flit∗f){ 16if(!_buffer_valid){ 17if(!_lock_box_valid){ 18/∗Progressdirectlytoarbiter∗/ 19_lock_box=f; 20_lock_box_valid=true; 21arb−>arbitrate(_lock_box,_id); 22}else{ 23/∗Progressdirectlytobuffer∗/ 24_buffer=f; 25_buffer_valid=true; 26} 27/∗Flitleftunlockbox∗/ 28nde−>unlock(_id,_dir); 29}else{ 30/∗Waitinunlockbox∗/ 31_unlock_box=f; 32_unlock_box_valid=true; 33} 34}
A.8 APPENDIX A SOURCE CODE
35 36voidgs_vc::unlock(){ 37if(_buffer_valid){ 38/∗Propagateflitfrombuffer∗/ 39_lock_box=_buffer; 40_buffer_valid=false; 41arb−>arbitrate(_lock_box,_id); 42 43/∗Possibleflitinunlock_boxmaynowpropagate∗/ 44if(_unlock_box_valid){ 45_buffer=_unlock_box; 46_buffer_valid=true; 47_unlock_box_valid=false; 48nde−>unlock(_id,_dir); 49} 50}else{ 51if(_unlock_box_valid){ 52/∗Propagateflitfromunlockbox∗/ 53_lock_box=_unlock_box; 54_unlock_box_valid=false; 55arb−>arbitrate(_lock_box,_id); 56nde−>unlock(_id,_dir); 57}else{ 58_lock_box_valid=false; 59} 60} 61} 62 63gs_vc::gs_vc(sc_core::sc_module_namen,constintid,const directiondir):vc(n),_id(id),_dir(dir){ 64_lock_box_valid=false; 65_buffer_valid=false; 66_unlock_box_valid=false; 67} A.2.7node.h 1#ifndef_NODE_H 2#define_NODE_H 3 4#include<systemc> 5#include"../types.h" 6#include"../interfaces.h" 7#include"arbiter.h"
8#include"vc.h" 9 10classnode:publicsc_core::sc_module,publicnode_transmitter_if, publicnode_receiver_if,publicnode_internal_if,public node_arbiter_if,publicnode_na_transmitter_if,public node_na_receiver_if{ 11 12public: 13sc_core::sc_port<link_transmitter_if>lnk_tx[4]; 14sc_core::sc_port<link_receiver_if>lnk_rx[4]; 15sc_core::sc_port<na_if>net_adap; 16 17/∗Send(receive)∗/ 18voidsend(flit∗); 19 20/∗Arbiter∗/ 21voidarb_send(flit∗,constdirection); 22voidarb_ready(constint,constdirection); 23 24/∗Externalunlocks∗/ 25voidunlock_gs(constint,constdirection); 26voidcredit_be(constint,constdirection); 27 28/∗InternalunlocksfromVCs∗/ 29voidunlock(constint,constdirection); 30voidcredit(constint,constdirection); 31 32/∗NetworkAdapter∗/ 33voidna_send(flit∗); 34voidna_unlock_gs(constint); 35 36/∗Initialisetables∗/ 37voidset_routing_table(direction∗,int∗); 38voidset_steer_table(direction∗,int∗); 39 40node(sc_core::sc_module_name,constsc_core::sc_time&); 41~node(); 42 43private: 44/∗Arbiterandvirtualchannels∗/ 45arbiter∗_arb[4]; 46vc∗_vcs[4][8]; 47 48/∗Routingtables∗/ 49direction_routing_dir[5][8];
COMPONENTS A.9
50int_routing_vc[5][8]; 51 52/∗Steertable∗/ 53direction_steer_dir[5][8]; 54int_steer_vc[5][8]; 55 56}; 57 58#endif A.2.8node.cpp 1#include"node.h" 2 3voidnode::send(flit∗f){ 4directiondf=f−>get_direction(); 5intvf=f−>get_vc(); 6/∗Lookupandsetnewdestination∗/ 7directiond=_routing_dir[(f−>get_direction()+2)%4][f−>get_vc() ]; 8intv=_routing_vc[(f−>get_direction()+2)%4][f−>get_vc()]; 9f−>set_direction(d); 10f−>set_vc(v); 11/∗Sendflittoitsdestination∗/ 12if(d==dir_local){ 13net_adap−>send(f); 14}else{ 15if(d>dir_local){ 16}else{ 17_vcs[f−>get_direction()][f−>get_vc()]−>send(f); 18} 19} 20} 21 22voidnode::arb_ready(constinti,constdirectiond){ 23_vcs[d][i]−>arb_ready(); 24} 25 26voidnode::arb_send(flit∗f,constdirectiond){ 27lnk_tx[d]−>send(f); 28} 29 30/∗Internal,fromVC∗/ 31voidnode::credit(constinti,constdirectiond){
32 33} 34 35/∗External,fromlink∗/ 36voidnode::credit_be(constinti,constdirectiond){ 37_vcs[d][i]−>unlock(); 38} 39 40/∗Internal,fromVC∗/ 41voidnode::unlock(constinti,constdirectiond){ 42if(_steer_dir[d][i]==dir_local){ 43net_adap−>unlock(_steer_vc[d][i]); 44}else{ 45if(_steer_dir[d][i]>dir_local||_steer_vc[d][i]>7){ 46}else{ 47lnk_rx[_steer_dir[d][i]]−>unlock_gs(_steer_vc[d][i]); 48} 49} 50} 51 52/∗External,fromlink∗/ 53voidnode::unlock_gs(constinti,constdirectiond){ 54/∗(d+2)%4calculatesthereversedirection∗/ 55_vcs[(d+2)%4][i]−>unlock(); 56} 57 58/∗NetworkAdapter∗/ 59voidnode::na_send(flit∗f){ 60/∗Lookupandsetdestination∗/ 61directiond=_routing_dir[dir_local][f−>get_vc()]; 62intv=_routing_vc[dir_local][f−>get_vc()]; 63f−>set_direction(d); 64f−>set_vc(v); 65if(d>dir_local){ 66}else{ 67_vcs[f−>get_direction()][f−>get_vc()]−>send(f); 68} 69} 70 71voidnode::na_unlock_gs(constinti){ 72if(_steer_dir[dir_local][i]>dir_local||_steer_vc[dir_local][ i]>7){ 73}else{ 74lnk_rx[_steer_dir[dir_local][i]]−>unlock_gs(_steer_vc[dir_local ][i]);
A.10 APPENDIX A SOURCE CODE
75} 76} 77 78/∗Initialisation∗/ 79voidnode::set_routing_table(direction∗dir,int∗vc){ 80for(inti=0;i<5;++i){ 81for(intj=0;j<8;++j,++dir,++vc){ 82_routing_dir[i][j]=∗dir; 83_routing_vc[i][j]=∗vc; 84} 85} 86} 87 88voidnode::set_steer_table(direction∗dir,int∗vc){ 89for(inti=0;i<5;++i){ 90for(intj=0;j<8;++j,++dir,++vc){ 91_steer_dir[i][j]=∗dir; 92_steer_vc[i][j]=∗vc; 93} 94} 95} 96 97node::node(sc_core::sc_module_namen,constsc_core::sc_time&lct) :sc_core::sc_module(n){ 98for(inti=0;i<4;++i){ 99_arb[i]=newarbiter(gen_unique_name("ARB",true),lct,i); 100_arb[i]−>nde(∗this); 101for(intj=0;j<8;++j){ 102_vcs[i][j]=newgs_vc(gen_unique_name("VC",true),j,i); 103_routing_dir[i][j]=(i+2)%4; 104_routing_vc[i][j]=j; 105_steer_dir[i][j]=(i+2)%4; 106_steer_vc[i][j]=j; 107((gs_vc∗)_vcs[i][j])−>nde(∗this); 108((gs_vc∗)_vcs[i][j])−>arb(∗(_arb[i])); 109} 110} 111} 112 113node::~node(){ 114for(inti=0;i<4;++i){ 115delete_arb[i]; 116for(intj=0;j<8;++j){ 117delete_vcs[i][j]; 118}
119} 120}
A.3 T est Files
A.3.1mango_thesis_model.h Thisisthetop-levelSystemCfile,whichcontainsthenetwork andtheconversionmodulestothenetworkadapters. 1/∗ 2Top−leveldesignfileformodelnetworkoftestsystem 3∗/ 4 5#ifndef_MANGO_THESIS_MODEL_H 6#define_MANGO_THESIS_MODEL_H 7 8#include<systemc> 9#include"na_conv.h" 10#include"link_sink.h" 11#include"../components/node.h" 12#include"../components/link.h" 13 14classmango_thesis_model:publicsc_core::sc_module{ 15 16public: 17/∗Initiator∗/ 18sc_core::sc_out<sc_dt::sc_lv<4>>RxReq_1; 19sc_core::sc_in<sc_dt::sc_lv<4>>RxAck_1; 20sc_core::sc_out<sc_dt::sc_lv<156>>RxData_1; 21sc_core::sc_out<sc_dt::sc_lv<4>>TxAck_1; 22sc_core::sc_in<sc_dt::sc_lv<4>>TxReq_1; 23sc_core::sc_in<sc_dt::sc_lv<156>>TxData_1; 24 25/∗Target∗/ 26sc_core::sc_out<sc_dt::sc_lv<4>>RxReq_2; 27sc_core::sc_in<sc_dt::sc_lv<4>>RxAck_2; 28sc_core::sc_out<sc_dt::sc_lv<156>>RxData_2; 29sc_core::sc_out<sc_dt::sc_lv<4>>TxAck_2; 30sc_core::sc_in<sc_dt::sc_lv<4>>TxReq_2; 31sc_core::sc_in<sc_dt::sc_lv<156>>TxData_2; 32TEST FILES A.11
33sc_core::sc_in<sc_dt::sc_logic>reset; 34 35SC_HAS_PROCESS(mango_thesis_model); 36 37mango_thesis_model(sc_core::sc_module_namen): 38sc_core::sc_module(n), 39na1("NA1"),na2("NA2"),lct(2.6,sc_core::SC_NS),sd(10.5, sc_core::SC_NS),ud(3.,sc_core::SC_NS), 40ls1n("LS1N"),ls1w("LS1W"),ls1s("LS1S"),ls2n("LS2N"),ls2e(" LS2E"),ls3w("LS3W"),ls3s("LS3S"),ls3e("LS3E"){ 41 42/∗Nodes∗/ 43nd1=newnode("ND1",lct); 44nd2=newnode("ND2",lct); 45nd3=newnode("ND3",lct); 46 47/∗Links∗/ 48lk12=newmango_link("LK12",dir_west,sd,ud,ud); 49lk21=newmango_link("LK21",dir_east,sd,ud,ud); 50lk23=newmango_link("LK23",dir_north,sd,ud,ud); 51lk32=newmango_link("LK32",dir_south,sd,ud,ud); 52 53/∗Deadendlinks∗/ 54ls1n.nde_tx(∗nd1);ls1n.nde_rx(∗nd1); 55ls1w.nde_tx(∗nd1);ls1w.nde_rx(∗nd1); 56ls1s.nde_tx(∗nd1);ls1s.nde_rx(∗nd1); 57ls2n.nde_tx(∗nd2);ls2n.nde_rx(∗nd2); 58ls2e.nde_tx(∗nd2);ls2e.nde_rx(∗nd2); 59ls3w.nde_tx(∗nd3);ls3w.nde_rx(∗nd3); 60ls3s.nde_tx(∗nd3);ls3s.nde_rx(∗nd3); 61ls3e.nde_tx(∗nd3);ls3e.nde_rx(∗nd3); 62 63/∗Connectinitiator∗/ 64na1.RxAck(RxAck_1); 65na1.RxReq(RxReq_1); 66na1.RxData(RxData_1); 67na1.TxAck(TxAck_1); 68na1.TxReq(TxReq_1); 69na1.TxData(TxData_1); 70na1.nde_tx(∗nd1); 71na1.nde_rx(∗nd1); 72 73/∗Connecttarget∗/ 74na2.RxAck(RxAck_2); 75na2.RxReq(RxReq_2);
76na2.RxData(RxData_2); 77na2.TxAck(TxAck_2); 78na2.TxReq(TxReq_2); 79na2.TxData(TxData_2); 80na2.nde_tx(∗nd3); 81na2.nde_rx(∗nd3); 82 83/∗Connectnodes∗/ 84nd1−>lnk_tx[dir_north](ls1n); 85nd1−>lnk_rx[dir_north](ls1n); 86nd1−>lnk_tx[dir_west](ls1w); 87nd1−>lnk_rx[dir_west](ls1w); 88nd1−>lnk_tx[dir_south](ls1s); 89nd1−>lnk_rx[dir_south](ls1s); 90nd1−>lnk_tx[dir_east](∗lk12); 91nd1−>lnk_rx[dir_east](∗lk21); 92nd1−>net_adap(na1); 93 94nd2−>lnk_tx[dir_north](ls2n); 95nd2−>lnk_rx[dir_north](ls2n); 96nd2−>lnk_tx[dir_east](ls2e); 97nd2−>lnk_rx[dir_east](ls2e); 98nd2−>lnk_tx[dir_west](∗lk21); 99nd2−>lnk_rx[dir_west](∗lk12); 100nd2−>lnk_tx[dir_south](∗lk23); 101nd2−>lnk_rx[dir_south](∗lk32); 102nd2−>net_adap(na1); 103 104nd3−>lnk_tx[dir_north](∗lk32); 105nd3−>lnk_rx[dir_north](∗lk23); 106nd3−>lnk_tx[dir_east](ls3e); 107nd3−>lnk_rx[dir_east](ls3e); 108nd3−>lnk_tx[dir_south](ls3s); 109nd3−>lnk_rx[dir_south](ls3s); 110nd3−>lnk_tx[dir_west](ls3w); 111nd3−>lnk_rx[dir_west](ls3w); 112nd3−>net_adap(na2); 113 114/∗Connectlinks∗/ 115lk12−>transmitter(∗nd1); 116lk12−>receiver(∗nd2); 117 118lk21−>transmitter(∗nd2); 119lk21−>receiver(∗nd1); 120
A.12 APPENDIX A SOURCE CODE
121lk23−>transmitter(∗nd2); 122lk23−>receiver(∗nd3); 123 124lk32−>transmitter(∗nd3); 125lk32−>receiver(∗nd2); 126 127/∗SetupinitiatorNAroutingtables∗/ 128directionna1dir[4]; 129na1dir[0]=dir_local; 130na1dir[1]=dir_local; 131na1dir[2]=dir_local; 132 133intna1vc[4]; 134na1vc[0]=0; 135na1vc[1]=1; 136na1vc[2]=2; 137 138na1.set_dir(na1dir); 139na1.set_vc(na1vc); 140 141/∗SetuptargetNAroutingtables∗/ 142directionna2dir[4]; 143na2dir[0]=dir_local; 144na2dir[3]=dir_local; 145 146intna2vc[4]; 147na2vc[0]=0; 148na2vc[3]=3; 149 150na2.set_dir(na2dir); 151na2.set_vc(na2vc); 152 153/∗Setupnode1routingtables∗/ 154directionnd1dir[5][8]; 155nd1dir[dir_local][0]=dir_east; 156nd1dir[dir_local][1]=dir_east; 157nd1dir[dir_local][2]=dir_east; 158nd1dir[dir_east][0]=dir_local; 159nd1dir[dir_east][7]=dir_local; 160 161intnd1vc[5][8]; 162nd1vc[dir_local][0]=7; 163nd1vc[dir_local][1]=0; 164nd1vc[dir_local][2]=3; 165nd1vc[dir_east][0]=1;
166nd1vc[dir_east][7]=0; 167 168/∗Setupnode1steertables∗/ 169directionnd1sdir[5][8]; 170nd1sdir[dir_local][0]=dir_east; 171nd1sdir[dir_local][1]=dir_east; 172nd1sdir[dir_local][2]=dir_east; 173nd1sdir[dir_local][3]=dir_east; 174nd1sdir[dir_east][0]=dir_local; 175nd1sdir[dir_east][7]=dir_local; 176 177intnd1svc[5][8]; 178nd1svc[dir_local][0]=7; 179nd1svc[dir_local][1]=0; 180nd1svc[dir_local][2]=1; 181nd1svc[dir_local][3]=1; 182nd1svc[dir_east][0]=1; 183nd1svc[dir_east][7]=0; 184 185nd1−>set_routing_table(&(nd1dir[0][0]),&(nd1vc[0][0])); 186nd1−>set_steer_table(&(nd1sdir[0][0]),&(nd1svc[0][0])); 187 188/∗Setupnode2routingtables∗/ 189directionnd2dir[5][8]; 190nd2dir[dir_west][7]=dir_south; 191nd2dir[dir_west][3]=dir_south; 192nd2dir[dir_west][0]=dir_south; 193nd2dir[dir_south][7]=dir_west; 194nd2dir[dir_south][2]=dir_west; 195 196intnd2vc[5][8]; 197nd2vc[dir_west][7]=7; 198nd2vc[dir_west][3]=5; 199nd2vc[dir_west][0]=0; 200nd2vc[dir_south][7]=7; 201nd2vc[dir_south][2]=0; 202 203/∗Setupnode2steertables∗/ 204directionnd2sdir[5][8]; 205nd2sdir[dir_south][7]=dir_west; 206nd2sdir[dir_south][5]=dir_west; 207nd2sdir[dir_south][0]=dir_west; 208nd2sdir[dir_west][7]=dir_south; 209nd2sdir[dir_west][0]=dir_south; 210
TEST FILES A.13
211intnd2svc[5][8]; 212nd2svc[dir_south][7]=7; 213nd2svc[dir_south][5]=3; 214nd2svc[dir_south][0]=0; 215nd2svc[dir_west][7]=7; 216nd2svc[dir_west][0]=2; 217 218nd2−>set_routing_table(&(nd2dir[0][0]),&(nd2vc[0][0])); 219nd2−>set_steer_table(&(nd2sdir[0][0]),&(nd2svc[0][0])); 220 221/∗Setupnode3routingtables∗/ 222directionnd3dir[5][8]; 223nd3dir[dir_north][7]=dir_local; 224nd3dir[dir_north][5]=dir_local; 225nd3dir[dir_north][0]=dir_local; 226nd3dir[dir_local][3]=dir_north; 227nd3dir[dir_local][0]=dir_north; 228 229intnd3vc[5][8]; 230nd3vc[dir_north][7]=0; 231nd3vc[dir_north][5]=2; 232nd3vc[dir_north][0]=1; 233nd3vc[dir_local][0]=7; 234nd3vc[dir_local][3]=2; 235 236/∗Setupnode3steertables∗/ 237directionnd3sdir[5][8]; 238nd3sdir[dir_local][0]=dir_north; 239nd3sdir[dir_local][2]=dir_north; 240nd3sdir[dir_local][1]=dir_north; 241nd3sdir[dir_local][3]=dir_north; 242nd3sdir[dir_north][7]=dir_local; 243nd3sdir[dir_north][2]=dir_local; 244 245intnd3svc[5][8]; 246nd3svc[dir_local][0]=7; 247nd3svc[dir_local][2]=5; 248nd3svc[dir_local][1]=0; 249nd3svc[dir_local][3]=6; 250nd3svc[dir_north][7]=0; 251nd3svc[dir_north][2]=3; 252 253nd3−>set_routing_table(&(nd3dir[0][0]),&(nd3vc[0][0])); 254nd3−>set_steer_table(&(nd3sdir[0][0]),&(nd3svc[0][0])); 255 256} 257 258~mango_thesis_model(){ 259deletend1,nd2,nd3,lk12,lk21,lk23,lk32; 260} 261 262private: 263node∗nd1; 264node∗nd2; 265node∗nd3; 266mango_link∗lk12; 267mango_link∗lk21; 268mango_link∗lk23; 269mango_link∗lk32; 270na_convna1,na2; 271link_sinkls1n,ls1w,ls1s,ls2n,ls2e,ls3w,ls3s,ls3e; 272sc_core::sc_timelct,sd,ud; 273 274}; 275 276#endif A.3.2mango_thesis_model.cpp 1#include"mango_thesis_model.h" 2 3#include<systemc.h> 4 5SC_MODULE_EXPORT(mango_thesis_model); A.3.3na_conv.h Thisfilecontainstheconversionmoduletothenetworkadapters. 1/∗ 2Conversionmodulefornetworkadapterstomodel 3∗/ 4 5#ifndef_NA_CONV_H 6#define_NA_CONV_H 7
A.14 APPENDIX A SOURCE CODE
8#include<systemc> 9#include"../interfaces.h" 10#include"../types.h" 11 12classna_conv:publicsc_core::sc_module,publicna_if{ 13 14public: 15/∗Ports∗/ 16sc_core::sc_out<sc_dt::sc_lv<4>>RxReq; 17sc_core::sc_in<sc_dt::sc_lv<4>>RxAck; 18sc_core::sc_out<sc_dt::sc_lv<156>>RxData; 19sc_core::sc_out<sc_dt::sc_lv<4>>TxAck; 20sc_core::sc_in<sc_dt::sc_lv<4>>TxReq; 21sc_core::sc_in<sc_dt::sc_lv<156>>TxData; 22 23/∗Signals∗/ 24sc_core::sc_signal<sc_dt::sc_logic>s_RxReq[4],s_RxAck[4], s_TxAck[4],s_TxReq[4]; 25sc_core::sc_signal<sc_dt::sc_lv<39>>s_RxData[4],s_TxData[4]; 26 27sc_core::sc_port<node_na_transmitter_if>nde_tx; 28sc_core::sc_port<node_na_receiver_if>nde_rx; 29 30SC_HAS_PROCESS(na_conv); 31 32/∗OnTxReqorRxAck∗/ 33voiddo_input(){ 34for(inti=0;i<4;++i){ 35s_TxData[i]=TxData.read().range(39∗(i+1)−1,39∗i); 36s_RxAck[i]=RxAck.read().get_bit(i); 37s_TxReq[i]=TxReq.read().get_bit(i); 38} 39} 40 41/∗OnTxAck,RxData∗/ 42voiddo_output(){ 43sc_dt::sc_lv<156>v_RxData; 44sc_dt::sc_lv<4>v_TxAck; 45for(inti=0;i<4;++i){ 46for(intj=0;j<39;++j){ 47v_RxData.set_bit(39∗i+j,s_RxData[i].read().get_bit(j)); 48} 49v_TxAck.set_bit(i,s_TxAck[i].read().value()); 50} 51RxData.write(v_RxData);
52TxAck.write(v_TxAck); 53_e.notify(1.5,sc_core::SC_NS); 54} 55 56/∗OnRxReq∗/ 57voiddo_delayed_output(){ 58sc_dt::sc_lv<4>v_RxReq; 59for(inti=0;i<4;++i){ 60v_RxReq.set_bit(i,s_RxReq[i].read().value()); 61} 62RxReq.write(v_RxReq); 63} 64 65/∗OnTxReq0,BE∗/ 66voiddo_TxReq_0(){ 67if(s_TxReq[0].posedge()){ 68if(!first_BE_flit){ 69/∗NotfirstBEflit∗/ 70TxReqQ[0]=(flit∗)(newflit_data<sc_dt::sc_lv<39>>( TxData.read().range(38,0),false)); 71TxReqQ[0]−>set_direction(_dir[0]); 72TxReqQ[0]−>set_vc(_vc[0]); 73nde_rx−>na_send(TxReqQ[0]); 74}else{ 75/∗FirstBEflit∗/ 76sc_dt::sc_lv<38>s_temp=TxData.read().range(37,0); 77s_temp.lrotate(10); 78sc_dt::sc_lv<39>s_temp2; 79s_temp2.set_bit(38,TxData.read().get_bit(38)); 80for(inti=0;i<38;++i){ 81s_temp2.set_bit(i,s_temp.get_bit(i)); 82} 83s_temp.set_bit(38,TxData.read().get_bit(38)); 84TxReqQ[0]=(flit∗)(newflit_data<sc_dt::sc_lv<39>>( s_temp,false)); 85TxReqQ[0]−>set_direction(_dir[0]); 86TxReqQ[0]−>set_vc(_vc[0]); 87nde_rx−>na_send(TxReqQ[0]); 88} 89/∗Updatefirst_BE_flit∗/ 90if(TxData.read().get_bit(38)==sc_dt::sc_logic(1)){ 91first_BE_flit=true; 92}else{ 93first_BE_flit=false; 94}
TEST FILES A.15
95}elseif(s_TxReq[0].negedge()){ 96/∗DelayforTxAckdeassert∗/ 97next_trigger(0.4,sc_core::SC_NS); 98}else{ 99/∗DeassertTxAck∗/ 100s_TxAck[0].write(s_TxReq[0].read()); 101} 102} 103 104/∗OnTxReq1,GS1∗/ 105voiddo_TxReq_1(){ 106if(s_TxReq[1].posedge()){ 107/∗Request∗/ 108TxReqQ[1]=(flit∗)(newflit_data<sc_dt::sc_lv<39>>(TxData. read().range(77,39),false)); 109TxReqQ[1]−>set_direction(_dir[1]); 110TxReqQ[1]−>set_vc(_vc[1]); 111nde_rx−>na_send(TxReqQ[1]); 112}elseif(s_TxReq[1].negedge()){ 113/∗TxReqdeasserted,delayforTxAck∗/ 114next_trigger(0.4,sc_core::SC_NS); 115}else{ 116/∗DeasserTxAck∗/ 117s_TxAck[1].write(s_TxReq[1].read()); 118} 119} 120 121/∗OnTxReq2,GS2∗/ 122voiddo_TxReq_2(){ 123if(s_TxReq[2].posedge()){ 124TxReqQ[2]=(flit∗)(newflit_data<sc_dt::sc_lv<39>>(TxData. read().range(116,78),false)); 125TxReqQ[2]−>set_direction(_dir[2]); 126TxReqQ[2]−>set_vc(_vc[2]); 127nde_rx−>na_send(TxReqQ[2]); 128}elseif(s_TxReq[2].negedge()){ 129next_trigger(0.4,sc_core::SC_NS); 130}else{ 131s_TxAck[2].write(s_TxReq[2].read()); 132} 133} 134 135/∗OnTxReq3,GS3∗/ 136voiddo_TxReq_3(){ 137if(s_TxReq[3].posedge()){
138TxReqQ[3]=(flit∗)(newflit_data<sc_dt::sc_lv<39>>(TxData. read().range(155,117),false)); 139TxReqQ[3]−>set_direction(_dir[3]); 140TxReqQ[3]−>set_vc(_vc[3]); 141nde_rx−>na_send(TxReqQ[3]); 142}elseif(s_TxReq[3].negedge()){ 143next_trigger(0.4,sc_core::SC_NS); 144}else{ 145s_TxAck[3].write(s_TxReq[3].read()); 146} 147} 148 149/∗OnRxAck0,BE∗/ 150voiddo_RxAck_0(){ 151if(s_RxAck[0].posedge()){ 152next_trigger(3.6,sc_core::SC_NS); 153}elseif(s_RxAck[0].negedge()){ 154nde_tx−>na_unlock_gs(0); 155}else{ 156s_RxReq[0].write(sc_dt::sc_logic(0)); 157} 158} 159 160/∗OnRxAck1,GS1∗/ 161voiddo_RxAck_1(){ 162if(s_RxAck[1].posedge()){ 163next_trigger(0.7,sc_core::SC_NS); 164}elseif(s_RxAck[1].negedge()){ 165nde_tx−>na_unlock_gs(1); 166}else{ 167s_RxReq[1].write(sc_dt::sc_logic(0)); 168} 169} 170 171/∗OnRxAck1,GS2∗/ 172voiddo_RxAck_2(){ 173if(s_RxAck[2].posedge()){ 174next_trigger(0.7,sc_core::SC_NS); 175}elseif(s_RxAck[2].negedge()){ 176nde_tx−>na_unlock_gs(2); 177}else{ 178s_RxReq[2].write(sc_dt::sc_logic(0)); 179} 180} 181
A.16 APPENDIX A SOURCE CODE
182/∗OnRxAck1,GS3∗/ 183voiddo_RxAck_3(){ 184if(s_RxAck[3].posedge()){ 185next_trigger(0.7,sc_core::SC_NS); 186}elseif(s_RxAck[3].negedge()){ 187nde_tx−>na_unlock_gs(3); 188}else{ 189s_RxReq[3].write(sc_dt::sc_logic(0)); 190} 191} 192 193/∗Flitarrivesfromnode∗/ 194voidsend(flit∗f){ 195flit_data<sc_dt::sc_lv<39>>∗fd=(flit_data<sc_dt::sc_lv<39> >∗)f; 196s_RxData[fd−>get_vc()].write(fd−>get_data()); 197s_RxReq[fd−>get_vc()].write(sc_dt::sc_logic(1)); 198deletef; 199} 200 201/∗Inittables∗/ 202voidset_dir(direction∗d){ 203for(inti=0;i<4;++i){ 204_dir[i]=∗(d+i); 205} 206} 207 208voidset_vc(int∗d){ 209for(inti=0;i<4;++i){ 210_vc[i]=∗(d+i); 211} 212} 213 214/∗Unlockchanneli∗/ 215voidunlock(constinti){ 216_e2[i].notify(5.1,sc_core::SC_NS); 217} 218 219voiddo_unlock0(){ 220s_TxAck[0].write(sc_dt::sc_logic(1)); 221} 222 223voiddo_unlock1(){ 224s_TxAck[1].write(sc_dt::sc_logic(1)); 225}
226 227voiddo_unlock2(){ 228s_TxAck[2].write(sc_dt::sc_logic(1)); 229} 230 231voiddo_unlock3(){ 232s_TxAck[3].write(sc_dt::sc_logic(1)); 233} 234 235na_conv(sc_core::sc_module_name){ 236SC_METHOD(do_input); 237sensitive<<RxAck<<TxReq; 238dont_initialize(); 239SC_METHOD(do_output); 240for(inti=0;i<4;++i){ 241sensitive<<s_RxReq[i]<<s_TxAck[i]<<s_RxData[i]; 242} 243dont_initialize(); 244SC_METHOD(do_TxReq_0); 245sensitive<<s_TxReq[0]; 246dont_initialize(); 247SC_METHOD(do_TxReq_1); 248sensitive<<s_TxReq[1]; 249dont_initialize(); 250SC_METHOD(do_TxReq_2); 251sensitive<<s_TxReq[2]; 252dont_initialize(); 253SC_METHOD(do_TxReq_3); 254sensitive<<s_TxReq[3]; 255dont_initialize(); 256SC_METHOD(do_RxAck_0); 257sensitive<<s_RxAck[0]; 258dont_initialize(); 259SC_METHOD(do_RxAck_1); 260sensitive<<s_RxAck[1]; 261dont_initialize(); 262SC_METHOD(do_RxAck_2); 263sensitive<<s_RxAck[2]; 264dont_initialize(); 265SC_METHOD(do_RxAck_3); 266sensitive<<s_RxAck[3]; 267dont_initialize(); 268SC_METHOD(do_delayed_output); 269sensitive<<_e; 270dont_initialize();
TEST FILES A.17
271SC_METHOD(do_unlock0); 272sensitive<<_e2[0]; 273dont_initialize(); 274SC_METHOD(do_unlock1); 275sensitive<<_e2[1]; 276dont_initialize(); 277SC_METHOD(do_unlock2); 278sensitive<<_e2[2]; 279dont_initialize(); 280SC_METHOD(do_unlock3); 281sensitive<<_e2[3]; 282dont_initialize(); 283s_RxData[0].write(sc_dt::sc_lv<39>(0)); 284s_RxData[1].write(sc_dt::sc_lv<39>(0)); 285s_RxData[2].write(sc_dt::sc_lv<39>(0)); 286s_RxData[3].write(sc_dt::sc_lv<39>(0)); 287s_RxReq[0].write(sc_dt::sc_logic(0)); 288s_RxReq[1].write(sc_dt::sc_logic(0)); 289s_RxReq[2].write(sc_dt::sc_logic(0)); 290s_RxReq[3].write(sc_dt::sc_logic(0)); 291 292first_BE_flit=true; 293} 294 295private: 296flit∗TxReqQ[4]; 297direction_dir[4]; 298int_vc[4]; 299sc_core::sc_event_e,_e2[4]; 300boolfirst_BE_flit; 301 302}; 303 304#endif A.3.4link_sink.h Thisfilecontainsamodulewhichsitsontheunconnectednode outputs.Itproducesawarningifitreceivesaflitoranunlock. 1/∗ 2Sinkfordeadendoutputsfromnodes 3∗/ 4 5#ifndef_LINK_SINK_H 6#define_LINK_SINK_H 7 8#include<systemc> 9#include"../interfaces.h" 10#include<ios> 11 12classlink_sink:publicsc_core::sc_module,public link_transmitter_if,publiclink_receiver_if{ 13 14public: 15/∗Ports∗/ 16sc_core::sc_port<node_transmitter_if>nde_tx; 17sc_core::sc_port<node_receiver_if>nde_rx; 18 19/∗Producewarningsifaccessed∗/ 20voidunlock_gs(inti){ 21std::cerr<<"Unlocksenttosink\n"; 22} 23 24voidcredit_be(inti){ 25std::cerr<<"Creditsenttosink\n"; 26} 27 28voidsend(flit∗f){ 29std::cerr<<"Flitsenttosink\n"; 30} 31 32link_sink(sc_core::sc_module_namen):sc_core::sc_module(n){} 33 34}; 35 36#endif A.3.5OCP_cores.h 1/∗ 2OCPcoresusedfortestsystem 3∗/ 4
A.18 APPENDIX A SOURCE CODE
5#ifndef_OCP_CORES_H 6#define_OCP_CORES_H 7 8#include<systemc> 9#include<iostream> 10 11/∗OCPMasterCommands∗/ 12constsc_dt::sc_lv<3>MCmd_idle(0); 13constsc_dt::sc_lv<3>MCmd_write(1); 14constsc_dt::sc_lv<3>MCmd_read(2); 15 16classOCP_cores:publicsc_core::sc_module{ 17 18public: 19//Masterports 20sc_core::sc_out<bool>M_OCPClk; 21sc_core::sc_out<sc_dt::sc_logic>M_Reset_n; 22sc_core::sc_out<sc_dt::sc_lv<3>>M_OCPMCmd; 23sc_core::sc_in<sc_dt::sc_logic>M_OCPSCmdAccept; 24sc_core::sc_out<sc_dt::sc_lv<32>>M_OCPMAddr; 25sc_core::sc_out<sc_dt::sc_lv<32>>M_OCPMData; 26sc_core::sc_out<sc_dt::sc_lv<8>>M_OCPMBurstLength; 27sc_core::sc_out<sc_dt::sc_lv<3>>M_OCPMBurstSeq; 28sc_core::sc_out<sc_dt::sc_logic>M_OCPMBurstSingleReq; 29sc_core::sc_out<sc_dt::sc_logic>M_OCPMBurstPrecise; 30sc_core::sc_out<sc_dt::sc_logic>M_OCPMReqLast; 31sc_core::sc_out<sc_dt::sc_logic>M_OCPMDataLast; 32sc_core::sc_out<sc_dt::sc_lv<2>>M_OCPMConnID; 33sc_core::sc_out<sc_dt::sc_lv<3>>M_OCPMThreadID; 34sc_core::sc_out<sc_dt::sc_logic>M_OCPMDataValid; 35sc_core::sc_in<sc_dt::sc_logic>M_OCPSDataAccept; 36sc_core::sc_in<sc_dt::sc_lv<2>>M_OCPSResp; 37sc_core::sc_out<sc_dt::sc_logic>M_OCPMRespAccept; 38sc_core::sc_in<sc_dt::sc_lv<32>>M_OCPSData; 39sc_core::sc_in<sc_dt::sc_logic>M_OCPSRespLast; 40sc_core::sc_in<sc_dt::sc_lv<3>>M_OCPSThreadID; 41sc_core::sc_out<sc_dt::sc_lv<3>>M_OCPMDataThreadID; 42sc_core::sc_in<sc_dt::sc_logic>M_OCPSInterrupt; 43 44//Slaveports 45sc_core::sc_out<bool>S_OCPClk; 46sc_core::sc_out<sc_dt::sc_logic>S_Reset_n; 47 48sc_core::sc_in<sc_dt::sc_lv<3>>S_OCPMCmd; 49sc_core::sc_out<sc_dt::sc_logic>S_OCPSCmdAccept;
50sc_core::sc_in<sc_dt::sc_lv<32>>S_OCPMAddr; 51sc_core::sc_in<sc_dt::sc_lv<32>>S_OCPMData; 52sc_core::sc_in<sc_dt::sc_logic>S_OCPMDataValid; 53sc_core::sc_out<sc_dt::sc_logic>S_OCPSDataAccept; 54sc_core::sc_in<sc_dt::sc_lv<8>>S_OCPMBurstLength; 55sc_core::sc_in<sc_dt::sc_lv<3>>S_OCPMBurstSeq; 56sc_core::sc_in<sc_dt::sc_logic>S_OCPMBurstSingleReq; 57sc_core::sc_in<sc_dt::sc_logic>S_OCPMBurstPrecise; 58sc_core::sc_in<sc_dt::sc_logic>S_OCPMReqLast; 59sc_core::sc_in<sc_dt::sc_logic>S_OCPMDataLast; 60sc_core::sc_in<sc_dt::sc_lv<2>>S_OCPMThreadID; 61sc_core::sc_in<sc_dt::sc_lv<2>>S_OCPMDataThreadID; 62sc_core::sc_out<sc_dt::sc_logic>S_OCPSRespLast; 63sc_core::sc_out<sc_dt::sc_lv<2>>S_OCPSThreadID; 64sc_core::sc_out<sc_dt::sc_lv<2>>S_OCPSResp; 65sc_core::sc_out<sc_dt::sc_lv<32>>S_OCPSData; 66sc_core::sc_in<sc_dt::sc_logic>S_OCPMRespAccept; 67sc_core::sc_out<sc_dt::sc_logic>S_OCPRespDone; 68sc_core::sc_out<sc_dt::sc_logic>S_OCPSInterrupt; 69 70voidocp_master(); 71voidocp_slave(); 72voidwr_m_clock(); 73voidwr_s_clock(); 74 75SC_HAS_PROCESS(OCP_cores); 76 77OCP_cores(sc_core::sc_module_name); 78 79/∗Clocks∗/ 80boolm_clock; 81bools_clock; 82 83/∗Smalldelay∗/ 84sc_core::sc_timech0in_speed; 85 86private: 87voidread_vectors(constchar∗,std::vector<sc_dt::sc_lv<76>>&); 88voiddo_ocp_master(sc_dt::sc_lv<76>,bool); 89voiddo_print(); 90 91/∗Testvectors∗/ 92std::vector<sc_dt::sc_lv<76>>prog_vecs; 93std::vector<sc_dt::sc_lv<76>>test_vecs; 94
TEST FILES A.19
95/∗Loggingoftransmissionandreceptiontimes∗/ 96std::vector<double>tm_time; 97std::vector<double>rs_time; 98std::vector<double>ts_time; 99std::vector<double>rm_time; 100sc_dt::sc_lv<76>idle_vec; 101boolint_done; 102sc_core::sc_timeint_time; 103 104/∗Disableclockstostopsimulation∗/ 105boolclk_enable; 106}; 107 108#endif A.3.6OCP_cores.cpp 1#include"OCP_cores.h" 2 3/∗OCPMaster∗/ 4voidOCP_cores::ocp_master(){ 5std::vector<sc_dt::sc_lv<76>>::iteratoriter; 6 7/∗Initialiseportvalues∗/ 8M_OCPMCmd.write(MCmd_idle); 9M_OCPMAddr.write(sc_dt::sc_lv<32>(0)); 10M_OCPMData.write(sc_dt::sc_lv<32>(0)); 11M_OCPMBurstLength.write(sc_dt::sc_lv<8>(1)); 12M_OCPMBurstSeq.write(sc_dt::sc_lv<3>(0)); 13M_OCPMBurstSingleReq.write(sc_dt::sc_logic(0)); 14M_OCPMBurstPrecise.write(sc_dt::sc_logic(0)); 15M_OCPMReqLast.write(sc_dt::sc_logic(0)); 16M_OCPMDataLast.write(sc_dt::sc_logic(0)); 17M_OCPMThreadID.write(sc_dt::sc_lv<3>(0)); 18M_OCPMDataValid.write(sc_dt::sc_logic(0)); 19M_OCPMConnID.write(sc_dt::sc_lv<2>(0)); 20M_OCPMRespAccept.write(sc_dt::sc_logic(0)); 21M_OCPMDataThreadID.write(sc_dt::sc_lv<3>(0)); 22 23M_Reset_n.write(sc_dt::sc_logic(1)); 24wait();wait(); 25wait();wait(); 26wait(ch0in_speed); 27 28/∗Reset∗/ 29M_Reset_n.write(sc_dt::sc_logic(0)); 30 31/∗Waitsometime∗/ 32wait();wait(); 33wait();wait(); 34wait();wait(); 35wait();wait(); 36wait();wait(); 37wait();wait(); 38wait();wait(); 39wait();wait(); 40wait();wait(); 41wait();wait(); 42wait();wait(); 43wait();wait(); 44 45wait(ch0in_speed); 46 47/∗Donereset∗/ 48M_Reset_n.write(sc_dt::sc_logic(1)); 49 50wait();wait(); 51wait();wait(); 52wait(ch0in_speed); 53 54//Programmingphase 55for(iter=prog_vecs.begin();iter!=prog_vecs.end();++iter){ 56do_ocp_master(∗iter,false); 57} 58 59//Waitphase 60do_ocp_master(idle_vec,false); 61for(inti=0;i<100;++i){ 62wait();wait(); 63} 64 65//Dataphase 66std::cout<<simcontext()−>time_stamp()<<":Networkprogrammed ...Activity\n"; 67intnr; 68for(nr=0,iter=test_vecs.begin();iter!=test_vecs.end(); ++iter,++nr){ 69if(nr%1000==0){ 70std::cout<<".";
A.20 APPENDIX A SOURCE CODE
71} 72do_ocp_master(∗iter,true); 73} 74std::cout<<"\n"; 75 76/∗Outputlogtofiles∗/ 77do_print(); 78 79/∗Stopsimulation∗/ 80clk_enable=false; 81std::cout<<"Simulationdone...stoping\n"; 82} 83 84/∗DooneOCPtransaction∗/ 85voidOCP_cores::do_ocp_master(sc_dt::sc_lv<76>vec,boolrecord){ 86/∗WriteMasterCommand∗/ 87M_OCPMCmd.write(vec.range(75,73)); 88 89if(vec.range(75,73)==MCmd_idle){ 90wait();wait(); 91wait(ch0in_speed); 92}elseif(vec.range(75,73)==MCmd_write){ 93M_OCPMConnID.write(vec.range(71,70)); 94M_OCPMThreadID.write(vec.range(68,66)); 95M_OCPMAddr.write(vec.range(64,33)); 96M_OCPMData.write(vec.range(31,0)); 97if(record){ 98tm_time.push_back(simcontext()−>time_stamp().to_double()); 99} 100wait();wait(); 101while(M_OCPSCmdAccept.read()!=sc_dt::sc_logic(1)){ 102wait();wait(); 103} 104 105wait(ch0in_speed); 106}elseif(vec.range(75,73)==MCmd_read){ 107M_OCPMConnID.write(vec.range(71,70)); 108M_OCPMThreadID.write(vec.range(68,66)); 109M_OCPMAddr.write(vec.range(64,33)); 110M_OCPMData.write(vec.range(31,0)); 111if(record){ 112tm_time.push_back(simcontext()−>time_stamp().to_double()); 113} 114wait();wait(); 115while(M_OCPSCmdAccept.read()!=sc_dt::sc_logic(1)){
116wait();wait(); 117} 118 119wait(ch0in_speed); 120M_OCPMCmd.write(MCmd_idle); 121 122//Waitforresponse 123while(M_OCPSResp.read()==sc_dt::sc_lv<2>(0)){ 124wait();wait(); 125} 126if(record){ 127rm_time.push_back(simcontext()−>time_stamp().to_double()); 128} 129M_OCPMRespAccept.write(sc_dt::sc_logic(1)); 130 131/∗Stopifrequestfailed∗/ 132if(M_OCPSResp.read()==sc_dt::sc_lv<2>(3)){ 133sc_core::sc_stop(); 134}elseif(M_OCPSResp.read()==sc_dt::sc_lv<2>(2)){ 135sc_core::sc_stop(); 136} 137while(M_OCPSResp.read()!=sc_dt::sc_lv<2>(0)){ 138wait(M_OCPSResp.default_event()); 139} 140M_OCPMRespAccept.write(sc_dt::sc_logic(0)); 141wait(ch0in_speed); 142} 143} 144 145 146/∗OCPSlaveCore∗/ 147voidOCP_cores::ocp_slave(){ 148/∗Initialiseportvalues∗/ 149S_OCPSCmdAccept.write(sc_dt::sc_logic(0)); 150S_OCPSDataAccept.write(sc_dt::sc_logic(0)); 151S_OCPSRespLast.write(sc_dt::sc_logic(0)); 152S_OCPSThreadID.write(sc_dt::sc_lv<2>(0)); 153S_OCPSResp.write(sc_dt::sc_lv<2>(0)); 154S_OCPSData.write(sc_dt::sc_lv<32>(0)); 155S_OCPRespDone.write(sc_dt::sc_logic(0)); 156S_OCPSInterrupt.write(sc_dt::sc_logic(0)); 157 158S_Reset_n.write(sc_dt::sc_logic(1)); 159 160wait();wait();
TEST FILES A.21
161wait();wait(); 162wait(ch0in_speed); 163 164/∗Reset∗/ 165S_Reset_n.write(sc_dt::sc_logic(0)); 166 167wait();wait(); 168wait();wait(); 169wait();wait(); 170wait();wait(); 171wait();wait(); 172wait();wait(); 173wait();wait(); 174wait();wait(); 175wait();wait(); 176 177wait(ch0in_speed); 178 179S_Reset_n.write(sc_dt::sc_logic(1)); 180/∗Resetdone∗/ 181 182wait();wait(); 183wait();wait(); 184 185/∗Waitfortransaction∗/ 186while(true){ 187wait(S_OCPMCmd.default_event()); 188if(S_OCPMCmd.read()==MCmd_idle){ 189}elseif(S_OCPMCmd.read()==MCmd_write){ 190rs_time.push_back(simcontext()−>time_stamp().to_double()); 191wait(ch0in_speed); 192S_OCPSCmdAccept.write(sc_dt::sc_logic(1)); 193S_OCPSThreadID.write(S_OCPMThreadID.read()); 194wait();wait(); 195wait(ch0in_speed); 196S_OCPSCmdAccept.write(sc_dt::sc_logic(0)); 197}elseif(S_OCPMCmd.read()==MCmd_read){ 198rs_time.push_back(simcontext()−>time_stamp().to_double()); 199wait(ch0in_speed); 200S_OCPSCmdAccept.write(sc_dt::sc_logic(1)); 201S_OCPSThreadID.write(S_OCPMThreadID.read().to_int()); 202wait();wait(); 203ts_time.push_back(simcontext()−>time_stamp().to_double()); 204wait(ch0in_speed); 205S_OCPSCmdAccept.write(sc_dt::sc_logic(0));
206S_OCPSData.write(S_OCPMAddr.read()); 207S_OCPSResp.write(sc_dt::sc_lv<2>(1)); 208S_OCPSRespLast.write(sc_dt::sc_logic(1)); 209while(S_OCPMRespAccept.read()!=sc_dt::sc_logic(1)){ 210wait();wait(); 211} 212wait(ch0in_speed); 213S_OCPSData.write(sc_dt::sc_lv<32>(0)); 214S_OCPSResp.write(sc_dt::sc_lv<2>(0)); 215S_OCPSRespLast.write(sc_dt::sc_logic(0)); 216}else{ 217/∗Unknowncommand∗/ 218} 219 220} 221} 222 223/∗OCPMasterclock,period4ns∗/ 224voidOCP_cores::wr_m_clock(){ 225m_clock=!m_clock; 226M_OCPClk.write(m_clock); 227if(clk_enable){ 228next_trigger(2.,sc_core::SC_NS); 229} 230} 231 232/∗OCPSlaveclock,period3ns∗/ 233voidOCP_cores::wr_s_clock(){ 234s_clock=!s_clock; 235S_OCPClk.write(s_clock); 236if(clk_enable){ 237next_trigger(1.5,sc_core::SC_NS); 238} 239} 240 241OCP_cores::OCP_cores(sc_core::sc_module_namen):sc_core:: sc_module(n),ch0in_speed(0.4,sc_core::SC_NS),idle_vec(0), int_time(2000,sc_core::SC_NS),int_done(false){ 242/∗Initialisevalues∗/ 243clk_enable=true; 244m_clock=false; 245s_clock=false; 246 247/∗Readprogrammingandtestvectors∗/ 248read_vectors("prog_vecs.in",prog_vecs);
A.22 APPENDIX A SOURCE CODE
249read_vectors("test_vecs.in",test_vecs); 250 251/∗Setupidlevector∗/ 252idle_vec.set_bit(72,sc_dt::sc_logic(1).value()); 253idle_vec.set_bit(69,sc_dt::sc_logic(1).value()); 254idle_vec.set_bit(65,sc_dt::sc_logic(1).value()); 255idle_vec.set_bit(32,sc_dt::sc_logic(1).value()); 256 257SC_THREAD(ocp_master); 258sensitive<<M_OCPClk; 259SC_THREAD(ocp_slave); 260sensitive<<S_OCPClk; 261SC_METHOD(wr_m_clock); 262SC_METHOD(wr_s_clock); 263} 264 265/∗Outputloggedtimestofiles∗/ 266voidOCP_cores::do_print(){ 267std::ofstreamreq("req_times.out"); 268std::ofstreamresp("resp_times.out"); 269std::vector<double>::const_iteratoriter1,iter2; 270 271 272if(!req.is_open()){ 273/∗Erroropeningfile∗/ 274} 275for(iter1=tm_time.begin(),iter2=rs_time.begin();iter1!= tm_time.end()&&iter2!=rs_time.end();++iter1,++iter2){ 276req<<(int)∗iter1<<""<<(int)∗iter2<<"\n"; 277} 278req.close(); 279 280 281if(!resp.is_open()){ 282/∗Erroropeningfile∗/ 283} 284for(iter1=ts_time.begin(),iter2=rm_time.begin();iter1!= ts_time.end()&&iter2!=rm_time.end();++iter1,++iter2){ 285resp<<(int)∗iter1<<""<<(int)∗iter2<<"\n"; 286} 287resp.close(); 288 289} 290 291/∗Readvectorsintov∗/
292voidOCP_cores::read_vectors(constchar∗fname,std::vector<sc_dt:: sc_lv<76>>&v){ 293charc; 294intnr=0; 295 296std::ifstreamf(fname); 297if(!f.is_open()){ 298std::cout<<"Erroropeningvectorfile"<<f<<"...stoping .\n"; 299sc_core::sc_stop(); 300return; 301} 302std::cout<<"Readingfile"<<fname<<"..."; 303while(!f.eof()){ 304sc_dt::sc_lv<76>tmp(0); 305for(inti=75;i>=0;−−i){ 306if(!(f>>c)){ 307f.close(); 308std::cout<<nr<<"entriesfound\n"; 309return; 310} 311tmp.set_bit(i,sc_dt::sc_logic(c).value()); 312} 313v.push_back(tmp); 314++nr; 315} 316f.close(); 317std::cout<<nr<<"entriesfound\n"; 318} 319 320#include<systemc.h> 321SC_MODULE_EXPORT(OCP_cores); A.3.7gen_test_vecs.cpp 1/∗ 2Smallprogramtogeneraterandomtestvectors 3∗/ 4 5#include<fstream> 6#include<iostream> 7#include<string> 8 9constintw0=0;