This section describes the customisation of the AVR_CORE microprocessor. The cus-tomisation includes changing the the RAM and ROM, implementation of the sleep modes and correction of bugs. To start with there will be a description of the Nimbus architecture.
3.2.1 Description of the Architecture Microprocessor
The microprocessor will be described in a top down approach. Figure 3.1 shows the top level of the microprocessor. At the top-level it is possible to see the internal clock the external clock, and the reset signal. The external clock is connected to the timer and the internal clock is connected to the sleep control unit. The sleep control module regulates the clock for the other parts of the system. The sleep control module is described in detail in section 3.2.3.
The core is placed in the middle of the figure and is connected to the instruction memory (ROM), data memory (RAM) and the I/O hardware components. The core
3.2 Customisation 23 is connected to the data memory and the I/O components through a common data bus. As described in the ATmega103 manual the I/O components memory is mapped.
Each component listen to the address signal to find out if the data on the bus is the component. The data bus is made as input and output signal to the core.
The I/O ports of the Nimbus microprocessor is placed in left part of the figure. In the top left corner just beneath the timer are the I/O pins for external interrupts. Then there are the UART and the two ports.
The I/O and interrupt component take care of the sequence of interrupt and which IO hardware component or the data memory has the right to write the data bus. The interrupts are arranged into a vector, so the microprocessor can handle multiple inter-rupts.
Timer Power
UART
PORTA
PORT B
CORE
ROM
RAM
IO & Interrupts control
Extern Clk
Extern Interrupts
Reset
Clock Gating
Interrupt
Clk
Clock Gating
Figure 3.1 Top level of the Nimbus design
In the listing below are names of the components, the belonging file and a short description of the component purpose. The source for the file can be found in appendix H.2.
• Top level (top_avr_core_rtl.vhd): Top-level design of the Nimbus microproces-sor.
• Package (AVRuCPackage.vhd):Constants and types.
• IO & Interrupts (external_mux.vhd):Data bus multiplexer and interrupt vector.
• IO & Interrupts (Service_Module.vhd):Special registers.
• IO & Interrupts (RAMDataReg.vhd):Data-bus register.
• ROM (rom_binary/ram16bit_XXX.vhd):This is the program memory where the XXX is the name of program.
24 Customised Synchronous AVR
• RAM (data_ram_rtl.vhd):Data RAM.
• Port A (porta.vhd):Parallel ports A.
• Port B (portb.vhd):Parallel ports B.
• Timer (Timer_Counter.vhd):Timer/Counter.
• Extra Timer (simple_timer.vhd):Simple timer.
• UART (uart.vhd):UART
• Sleep Control (power_control.vhd):Sleep mode control.
Core
The core is the main part of the Nimbus microprocessor. Figure 3.2 shows the connec-tions between different components in the core.
pm_fetch_dec
reg_file io_reg_file io_adr_dec dbusin
inst
irq_lines
pc inst_req
adr
iowe iore
dbusout
irqack
sleep_sleep_enable irqackad alu_avr bit_processor
clk reset Nimbus Core
Figure 3.2 The structure of the Nimbus core.
• CORE (avr_core.vhd):top-level design of AVR core.
• ALU (alu_avr.vhd):ALU.
• Bit processor (bit_processor.vhd):The Bit processor is used for bitwise operation like XOR.
• Register file (reg_file.vhd):Register file.
• Decode (pm_fetch_dec.vhd):Includes program counter, instruction decoder, mem-ory and I/O memmem-ory.
• IO Register file (io_reg_file.vhd):I/O registers.
• IO Address Decode (io_adr_dec.vhd): Address decoder and data bus multi-plexer for the I/O registers.
3.2.2 ROM & RAM
The ROM and RAM specification has been chanced to a VHDL description that is sup-ported by Xilinx XST standard 3.4.1. The size of the RAM has chanced from 128Byte to 4096Bytes and the size of ROM depends on program 3.4.1.
3.2 Customisation 25 The ROM reads and RAM reads and writes are not done on the event when the clock signal becomes zero. Before the ROM and RAM were accessed asynchronously.
3.2.3 Sleep Mode
The sleep mode for the Nimbus microprocessor has been implemented as described in the ATmega103 documentation. The difference between the ATmega128 and AT-mega103 is that ATAT-mega103 does not support the standby functions as described in section 2.1.4.
The sleep mode is implemented in form of clock-gating. The sleep instruction is executed, the sleep mode state machine looks in the sleep mode register. If theidle mode is set, the clock for the Core, RAM and ROM is stopped. This means that inter-rupts from external interrupt, the timer, ports or UART can wake the microprocessor up.
ThePower-Savemode stops all the components except the timer and the external interrupt and the Power-Down mode stops everything so only an external interrupt can wake up the system.
On figure 3.1 it is possible to see the top level of the Nimbus microprocessor. The green signal is the clock for the Core, RAM and ROM, the blue signal is the clock for the I/O and the purple is the clock signal for the timer.
The clock stops when the clock signal is low. The clock is first enable when the internal clock goes high afters an interrupt. Every component then functions normally again. The clock starts and stops in this way to avoid that the clock period is too small.
The way the sleep model is implemented in the Nimbus microprocessor is more like the standby sleep mode in the ATmega128. The power down and power save sleep modes for the ATmega128 turns off the oscillator and when it is turned on, it takes a long time for the clock to be stable again. The standby mode is not available in the ATmega103.
3.2.4 Identified Bugs
Only a few bugs were found, but these were very essential. Some of the bugs were described in [29] and they were wiped out. The bugs caused an incorrect handling of the following instructions:
• push and pop instruction: The data write was done and address were set too early. (push)
• ld rD, Yandld rD, Zinstruction: The instructions were not detected.
• st rD, Yandst rD, Zinstruction: The instruction were not detected.
• ld rD, X+ and ld rD, -X instruction: The post increment (X+) and pre-decrement (-X) were not detected.
• bst Rd,b instruction: There was an internal error where the instruction was mistaken for thebsetinstruction.
In addition to these bug there were found the following bugs:
• retiinstruction: Too early calculation of return address.
26 Customised Synchronous AVR
• popinstruction: The load address was wrong.
The interrupts were also handle wrong. The current program counter was calcu-lated too early.
All these errors mean that the AVR_CORE could only have been tested using logical instructions. The problems with these bugs are, that there has never been tested com-plected programs on the AVR_CORE. This would have lead to detection of the bugs.