Current Measurements on Reset

The next experiment was a measurement of the current consumption of the 100 chips. The purpose of the experiment was to check if the chips consumed a reasonable amount of power when clocked at varying frequencies. Further-more, the responses of the chips on a reset procedure were observed: First, the voltage levels of four output pins were measured while the reset signal was activated. Then, the voltage levels were measured while the reset signal was deactivated. This gave a first indication of the functionality of the chips.

A simple test board, using an adjustable clock generating circuit, was built. The frequency of the system clock signal was set up via the parallel interface port from a Personal Computer (PC). Except from the reset signal and the system clock signal, all of the input pins were connected to either Vdd (5 V) or GND (0 V), giving a proper configuration of the processor. The processor was configured to use the so-called general purpose (GP) interface.

1. The measurements of voltage levels were done on the four output pins denoted by outputData, doneKey, doneExp and errorsync in the de-scription in Appendix E. Pin outputDatais the data output from the

4.4. TEST AND PERFORMANCE 155 I/O register. This pin is the only tristate output pin of the processor.

DoneKey is a flag that signals the end of an initialisation procedure.

This procedure is performed by the processor each time new values of the modulus and the exponent have been shifted into the processor.

DoneExp is a flag that signals the end of an exponentiation process.

Finally, errorSync is a flag that signals the detection of an error in the synchronisation pattern used in the self-synchronising SLD interface (see Appendix E). The correct voltage levels of the pins are shown in Table 4.1. Note that pin outputData is in the high impedance state, denoted byZ, when the reset signal is active. (The reset signal is active at a low voltage level). To check the high impedance of the outputData pin, the voltage level was forced to high through a pull up resistance and, similarly, forced to low through a pull down resistance.

Reset OutputData DoneKey DoneExp ErrorSync

0 Z 0 5 5

5 0 5 5 0

Table 4.1: Correct voltage levels of observed output pins.

2. Simultaneously with keeping the reset signal at the active level, the cur-rent consumption was measured at three clocking frequencies, 5 MHz, 10 MHz and 20MHz. During an activation of the reset signal, the con-trol unit is brought into a well-defined state. In this state, some of the registers are cleared, and all of the remaining registers are holding their values. Consequently, the current consumed by the combinato-rial circuitry between the registers will be minimal and, therefore, the influence on the current measurements from the (unknown) values in the registers after power-up will be relatively low.² It was expected to

2None of the combinatorial circuit cells are using dynamic logic families, where an internal node is pre-charged before the evaluation of the output values. Therefore, the current consumed by these cells is independent of the actual input values. However, the registers are using a type of D flip-flops [YS89], where an internal node is pre-charged in each clock period. Depending on the actual value held by the flip-flop, this internal node will be discharged in each clock period as well. In fact, if the value held by the flip-flop is zero, this internal node will alternately be charged and discharged. If the value is one, the node will remain charged. So, to some extent, the current measurements will be

see a linear relationship between the current consumptionitotal and the clocking frequency fΩ of the form

itotal =istatic+fΩ·idynamic (4.4) The static current istatic is the contribution from leakages in the cir-cuitry and from the output pins of the processor. Furthermore, there is a contribution from the test board. (This contribution was mea-sured, without a processor in the test board, to be 256 µA when the reset signal was activated, and 40µAwhen deactivated.) The dynamic currentidynamicis the contribution from the circuitry for distribution of the clock signal and from the flip-flops clocked by this signal. The cur-rent supply to the external circuit for generating the clock signal was separated from the supply to the remaining parts of the test board.

Hence, the current contribution from the clock generation circuit was excluded from the measurements.

3. Finally, after deactivating the reset signal, the current consumption was measured at a 20 MHz clocking frequency. This current is a measure of the power consumption when the processor is idle, i.e. in a state where the processor is ready for further processing. The internal operation of the processor, just prior to the event of deactivating the reset signal and just after this event, only differs in one respect: No registers are being actively cleared. However, since all registers are holding their values, the cleared registers will remain cleared.

The current measurements, and the observation of the voltage levels of the four output pins, implied that 17 chips were classified as failing chips: All of these chips consumed a current, that was significantly larger than the other 83 chips. Furthermore, some of the failing chips had erroneous voltage levels at the output pins. The difference in current consumption was most significant for the measurements at the 5 MHz clocking frequency, and least significant

influenced by the power-up state of the registers. Some of the registers are using a flip-flop variant that can be cleared, i.e. the value held by such a flip-flop can be forced to zero by activation of a “clear” input signal. When this signal is activated, the above mentioned internal node will remain discharged throughout a clocking period, and the pre-charging is disabled. Approximately 1,200 of the flip-flops have this clear option. When the external reset signal is activated, the clear signal for these flip-flops is activated, and when the reset signal is deactivated, the clear signal is deactivated, as well.

4.4. TEST AND PERFORMANCE 157 for the 20 MHz frequency. This indicated a large static current consumption for the failing chips, and it may be a symptom of, unintentionally, shorted circuitry in the chips.

Figure 4.13: Plot of current as function of clocking frequency.

Two plots of the current measurements, with an active reset signal, for the remaining 83 chips are shown in Figure 4.13. The plot on the left comprises all 83 chips, while the plot on the right is limited to the data for the 8 working chips. Except from two sets of data in the left plot, all sets of data show an approximately linear relation between the current consumption and the clocking frequency. Furthermore, it is seen that the slopes of the lines are almost identical for the vast majority of the chips. So, assuming that the current consumption is given by expression (4.4), it is seen that the variation in current consumption of the chips are mainly due to variations in the static current consumption. The plot of the currents for the working chips shows a small variation in the static current consumption, and a small variation in the dynamic current consumption.

The current measurements for the 8 working chips are listed in Table

Chip No. 5 MHZ 10 MHZ 20 MHZ 20 MHZ, non-reset istatic idynamic

mA mA mA mA mA mA/MHz

01 25.2 49.7 97.0 107.6 1.6 4.8

11 25.7 50.5 98.7 109.4 1.6 4.9

15 24.8 48.8 95.4 105.8 1.5 4.7

37 25.7 50.5 98.6 109.4 1.7 4.9

53 25.3 49.7 97.2 107.8 1.6 4.8

63 25.6 50.4 98.6 109.3 1.5 4.9

66 26.1 51.0 99.2 110.0 2.0 4.9

89 25.4 50.0 97.7 108.4 1.6 4.8

Table 4.2: Current consumption of working chips

4.2. The first column contain the identification numbers of the chips. The next three columns lists the current measurements when the reset signal was at the active level. The fifth column contains the single measurement done when the reset signal was deactivated. Finally, in the last two columns, some estimated values of the static current and of the dynamic current are computed. These values are obtained by fitting a line, expressed by (4.4), to the three measurements of the current when the reset signal was active. It is seen that the static current for the working chips is in the range from 1.5 mA to 2.0 mA, and the dynamic current is in the range from 4.7 mA/MHz to 4.9 mA/Hz. A similar computation for the other 83−8 = 75 chips confirms that the dynamic current is about equal for the vast majority of the chips:

Of the 83 chips, 75 have a dynamic current in the same range as the working chips. The static current of the 83 chips shows a much larger variation: It varies from 1.4 mA to 30.2 mA, and the number of chips, having a static current in the same range as the working chips, is 37. Hence, it seems like this relatively simple measurements of currents might be a suitable method to classify the sample of chips into a class of candidates for working chips and a class of definitely failing chips. In this case, the method would classify approximately 60 percents of the chips as failing.

According to measurements at the 20 MHz clocking frequency in Table 4.2, the current consumption increases by 10.4–10.8 mA when the reset signal is deactivated. This is due to the internal operation of about 1,200 flip-flops that are no longer being actively cleared and, therefore, consume current through a process of pre-charging and discharging an internal node.

4.4. TEST AND PERFORMANCE 159