PBAD_Tet Ara aTc
mRNA_CI CI
P_YFP mRNA_YFP YFP
P_YFP_bound aTc_p
ara_p
tc_CI
tl_CI
decay_mRNA_CI decay_CI
tc_YFP tl_YFP
decay_mRNA_YFP decay_YFP bind_YFP_CI
Figure 7.6: SPN of genetic NOR-gate.
clearly shows that there is a coherence between our and Snoopy’s implementa-tion. Stochastic simulations can of course not be completely identical, but the overall behaviour is clearly identical, with Snoopy’s simulations consequently having concentration levels somewhat under our simulations.
Note that this verification is by no means thorough, as we have presented the formalities of Gillespie’s algorithm in previous chapters, and our implementation of it is not efficient but usable.
7.7 Concluding remarks
In this chapter we have seen how the DTU-SB Framework has been imple-mented with modularity and extensibility in mind. The framework can be used as library for third-party applications or it can be used as standalone application either by using it from the command-line or by using the graphical
0 2,000 4,000 6,000
(a)The numbers in the parenthesises in the legends indicate the number of it-erations per simulation.
(b)One simulation with 10 iterations.
Figure 7.7: The graph in(a)contains two simulations of the NOR-gate with no Ara or aTc present, thus YFP is high.
The graph in(b) contains one simulation of the NOR-gate with aTc present, this YFP is low.
0 2,000 4,000 6,000
(a)This graph is directly comparable to the graph in Fig. 7.7a.
0 2,000 4,000 6,000
(b)This graph is directly comparable to the graph in Fig. 7.7b.
Figure 7.8: Simulations with Snoopy.
user interface provided. As mentioned the code repository is located athttps:
//bitbucket.org/jboysen/dtu-sband the documentation for the framework can be found athttp://jboysen.github.io/dtu-sb-docs. To get a head start by avoiding to set up development environments and compilation of java-files the file DTU-SB-GUI.zipcontaining a pre-compiled JAR-file with belonging li-brary of small genetic devices can be downloaded athttps://bitbucket.org/
jboysen/dtu-sb/downloads.
The implementation of Gillespie’s direct SSA has been evaluated by comparing
7.7 Concluding remarks 75
simulations of devices with simulations of the same devices using Snoopy. The evaluation is by no means thorough but purely serve the purpose of establishing confidence in our implementation.
In the next chapter Genetic Logic Synthesis will be explained thoroughly, and the results of it has been incorporated into the framework as well, see Appendix D for a tutorial on this matter.
Chapter 8
Genetic Logic Synthesis
The theory established in the preceding chapters will here be utilised to per-form genetic design automation (GDA) so that systems of genetic devices can be synthesised automatically using a logic function as target and a library of pre-defined genetic devices. The main idea is to perceive each genetic device as a logical gate that can be specified by a truth-table where low and high respec-tively represent absence or presence of certain proteins . These devices are then combined to express the target-function. Such abstractions are not unrealistic, e.g. Bonnet et al.(2013) have shown how several genetic devices quite precisely followed their predicted logical behaviour.
Perceiving the genetic behaviour logically allows us to reuse the widely devel-oped theory for electronic design automation (EDA). Further the desired ap-plications for synthetic biology are something that is often easily expressible as logical problems, for example the biosensor that detects presence of certain combinations of material and takes action accordingly (whether that is emitting fluorescent material signalling the need for external intervention or synthesising material that can react in-place).
Different genes with different promoters can have widely different activation levels why it is not immediately clear what the concentration levels of absence or presence specifically represent for a set of genetic devices. The examples throughout this chapter all assume compatible concentration levels where the
general case will be discussed further in Sec. 8.6.
This chapter will first establish a suitable level of abstraction while explaining an overall approach to the problem, then propose a simple prototype method while explaining the similarities to EDA tools and finally discuss how this could be improved.
8.1 Logic synthesis
In electronics, logic synthesis is the process where a high-level description of a design is converted into an optimised composition of gates found in a given library, these gates are typically referred to as library parts or just parts. The composition is found using atechnology mapper,and the high-level description can be specified as e.g. a truth-table. Typically some optimisation can be done on the high-level description by minimising the expression.
Both of these steps might output several design candidates, so objective func-tions are used to evaluate the order from best to worst according to some given criteria. The theory behind minimisation and technology mapping have roots in digital electronics where commercial VHDL and Verilog IDE’s such asAltera andXilinxemploy these techniques to either minimise or promote factors such ascost, delay, die-area, speed and fault-tolerancy of a given chip design. Often the actual synthesis engines used in these tools are both more efficient and more sophisticated than those presented here.