Bus architecture - Multiprocessor in a FPGA

152 HDL files

31rst_i:inbit_t; 32tx:outstd_logic;--RS232TX 33rx:instd_logic;--RS232RX 34running:outbit_t 35); 36endcomponent; 37 38SIGNALclk:bit_t; 39SIGNALreset:bit_t; 40SIGNALtx:bit_t; 41SIGNALrx:bit_t; 42SIGNALrunning:bit_t; 43 44begin 45 46thesystem:soc_bus 47portmap( 48clk_i=>clk, 49rst_i=>reset, 50tx=>tx, 51rx=>’1’, 52running=>running 53); 54 55 56process 57begin--process 58reset<=’0’; 59waitfor105ns; 60reset<=’1’; 61waitfor1005ns; 62reset<=’0’; 63waitfor105ns; 64reset<=’1’; 65wait; 66endprocess;

A.4 Bus architecture 153

67 68clock:process 69begin--processclock 70clk<=’0’; 71waitfor5ns; 72clk<=’1’; 73waitfor5ns; 74endprocessclock; 75 76 77 78 79endstruc;

154 HDL files

A.4.2 con bus so c.vhd

1-------------------------------------------------------------------- 2-- 3--SoCdesignformultiprocessor 4--Editor:NikolajTørring-s042505 5--Version:1.0 6--Datalastmodified:25/4-2007 7-- 8--------------------------------------------------------------------- 9-- 10--VersionHistory 11-- 12--v1.0:Firstworkingversion 13-- 14--------------------------------------------------------------------- 15 16libraryIEEE; 17useIEEE.std_logic_1164.ALL; 18useIEEE.std_logic_arith.ALL; 19usework.types.all; 20libraryUNISIM; 21useUNISIM.all; 22 23entitysoc_busis 24 25port( 26clk_i:instd_logic; 27rst_i:instd_logic; 28tx:outstd_logic; 29rx:instd_logic; 30running:outstd_logic); 31 32endsoc_bus; 33 34architecturestrucofsoc_busis

A.4 Bus architecture 155

35 36componentor1200_top 37generic( 38dw:integer:=32; 39aw:integer:=32; 40ppic_ints:integer:=20 41); 42port( 43clk_i:instd_logic; 44rst_i:instd_logic; 45pic_ints_i:instd_logic_vector(ppic_ints-1downto0); 46clmode_i:instd_logic_vector(1downto0); 47 48--InstructionWISHBONEinterface 49iwb_clk_i:instd_logic; 50iwb_rst_i:instd_logic; 51iwb_ack_i:instd_logic; 52iwb_err_i:instd_logic; 53iwb_rty_i:instd_logic; 54iwb_dat_i:instd_logic_vector(31downto0); 55iwb_cyc_o:outstd_logic; 56iwb_adr_o:outstd_logic_vector(31downto0); 57iwb_stb_o:outstd_logic; 58iwb_we_o:outstd_logic; 59iwb_sel_o:outstd_logic_vector(3downto0); 60iwb_dat_o:outstd_logic_vector(31downto0); 61iwb_cab_o:outstd_logic; 62 63--DataWISHBONEinterface 64dwb_clk_i:instd_logic; 65dwb_rst_i:instd_logic; 66dwb_ack_i:instd_logic; 67dwb_err_i:instd_logic; 68dwb_rty_i:instd_logic; 69dwb_dat_i:instd_logic_vector(31downto0); 70dwb_cyc_o:outstd_logic;

156 HDL files

71dwb_adr_o:outstd_logic_vector(31downto0); 72dwb_stb_o:outstd_logic; 73dwb_we_o:outstd_logic; 74dwb_sel_o:outstd_logic_vector(3downto0); 75dwb_dat_o:outstd_logic_vector(31downto0); 76dwb_cab_o:outstd_logic; 77 78--Debuginterface 79dbg_stall_i:instd_logic; 80dbg_ewt_i:instd_logic; 81dbg_lss_o:outstd_logic_vector(3downto0); 82dbg_is_o:outstd_logic_vector(1downto0); 83dbg_wp_o:outstd_logic_vector(10downto0); 84dbg_bp_o:outstd_logic; 85dbg_stb_i:instd_logic; 86dbg_we_i:instd_logic; 87dbg_adr_i:instd_logic_vector(31downto0); 88dbg_dat_i:instd_logic_vector(31downto0); 89dbg_dat_o:outstd_logic_vector(31downto0); 90dbg_ack_o:outstd_logic; 91 92--PowerManagementinterface 93pm_cpustall_i:instd_logic; 94pm_clksd_o:outstd_logic_vector(3downto0); 95pm_dc_gate_o:outstd_logic; 96pm_ic_gate_o:outstd_logic; 97pm_dmmu_gate_o:outstd_logic; 98pm_immu_gate_o:outstd_logic; 99pm_tt_gate_o:outstd_logic; 100pm_cpu_gate_o:outstd_logic; 101pm_wakeup_o:outstd_logic; 102pm_lvolt_o:outstd_logic 103); 104endcomponent; 105 106componentcore_mem

A.4 Bus architecture 157

107port( 108--I/OPorts 109wb_clk_i:inbit_t;--TheClock 110wb_rst_i:inbit_t;--Theresetsignal 111 112--WBslavei/f 113wb_data_i:inword_t;--WBdatain 114wb_data_o:outword_t;--WBdataout 115wb_adr_i:inword_t;--WBadress 116wb_sel_i:instd_logic_vector(3downto0);--WBselectinputarray 117wb_we_i:inbit_t;--WBwriteenable 118wb_cyc_i:inbit_t;--WBcycleinput 119wb_stb_i:inbit_t;--WBstrobeinput 120wb_ack_o:outbit_t;--WBacknowledgeoutput 121wb_err_o:outbit_t);--WBerrorsignal 122endcomponentcore_mem; 123 124componentsemaphore 125port( 126--I/OPorts 127wb_clk_i:inbit_t;--TheClock 128wb_rst_i:inbit_t;--Theresetsignal 129 130--WBslavei/f 131wb_data_i:inword_t;--WBdatain 132wb_data_o:outword_t;--WBdataout 133wb_adr_i:inword_t;--WBadress 134wb_sel_i:instd_logic_vector(3downto0);--WBselectinputarray 135wb_we_i:inbit_t;--WBwriteenable 136wb_cyc_i:inbit_t;--WBcycleinput 137wb_stb_i:inbit_t;--WBstrobeinput 138wb_ack_o:outbit_t;--WBacknowledgeoutput 139wb_err_o:outbit_t);--WBerrorsignal 140endcomponentsemaphore; 141 142componentuart_top

158 HDL files

143port( 144--I/OPorts 145wb_clk_i:inbit_t;--TheClock 146 147--WBslavesignal 148wb_rst_i:inbit_t;--Theresetsignal 149wb_adr_i:instd_logic_vector(4downto0);--WBadress 150wb_dat_i:inword_t;--WBdatain 151wb_dat_o:outword_t;--WBdataout 152wb_we_i:inbit_t;--WBwriteenable 153wb_stb_i:inbit_t;--WBstrobeinput 154wb_cyc_i:inbit_t;--WBcycleinput 155wb_ack_o:outbit_t;--WBacknowledgeoutput 156wb_sel_i:instd_logic_vector(3downto0);--WBselectinputarray 157 158int_o:outbit_t;--interruptrequest 159 160--UARTsignals 161--serialinput/output 162stx_pad_o:outbit_t;--Transmitdata 163srx_pad_i:inbit_t;--ReciveData 164 165--modemsignals 166rts_pad_o:outbit_t;--Requesttosend 167cts_pad_i:inbit_t;--Cleartosend 168dtr_pad_o:outbit_t;-- 169dsr_pad_i:inbit_t;--Datasetready 170ri_pad_i:inbit_t;--Ringindicator 171dcd_pad_i:inbit_t--DataCarrierDetect 172); 173 174endcomponentuart_top; 175 176componentwb_conbus_top 177generic( 178--Imem0x00000000

A.4 Bus architecture 159

179s0_addr_w:integer:=17; 180--s0_addr:integer:=0; 181s0_addr:integer:=0; 182--Dmem0x00004000 183s1_addr_w:integer:=17; 184--s1_addr:integer:=8192; 185s1_addr:integer:=1; 186s27_addr_w:integer:=8; 187--UART0x90000000 188--s2_addr:integer:=-1879048192; 189s2_addr:integer:=144; 190--Semaphore0x40000000 191--s3_addr:integer:=1073741824; 192s3_addr:integer:=64; 193--Notused 194s4_addr:integer:=27; 195s5_addr:integer:=28; 196s6_addr:integer:=29; 197s7_addr:integer:=30 198); 199port( 200 201--I/Oports 202clk_i:instd_logic; 203rst_i:instd_logic; 204 205--Master0 206m0_dat_i:instd_logic_vector(31downto0); 207m0_dat_o:outstd_logic_vector(31downto0); 208m0_adr_i:instd_logic_vector(31downto0); 209m0_sel_i:instd_logic_vector(3downto0); 210m0_we_i:instd_logic; 211m0_cyc_i:instd_logic; 212m0_stb_i:instd_logic; 213m0_ack_o:outstd_logic; 214m0_err_o:outstd_logic;

160 HDL files

215m0_rty_o:outstd_logic; 216m0_cab_i:instd_logic; 217 218--Master1 219m1_dat_i:instd_logic_vector(31downto0); 220m1_dat_o:outstd_logic_vector(31downto0); 221m1_adr_i:instd_logic_vector(31downto0); 222m1_sel_i:instd_logic_vector(3downto0); 223m1_we_i:instd_logic; 224m1_cyc_i:instd_logic; 225m1_stb_i:instd_logic; 226m1_ack_o:outstd_logic; 227m1_err_o:outstd_logic; 228m1_rty_o:outstd_logic; 229m1_cab_i:instd_logic; 230 231--Master2 232m2_dat_i:instd_logic_vector(31downto0); 233m2_dat_o:outstd_logic_vector(31downto0); 234m2_adr_i:instd_logic_vector(31downto0); 235m2_sel_i:instd_logic_vector(3downto0); 236m2_we_i:instd_logic; 237m2_cyc_i:instd_logic; 238m2_stb_i:instd_logic; 239m2_ack_o:outstd_logic; 240m2_err_o:outstd_logic; 241m2_rty_o:outstd_logic; 242m2_cab_i:instd_logic; 243 244--Master3 245m3_dat_i:instd_logic_vector(31downto0); 246m3_dat_o:outstd_logic_vector(31downto0); 247m3_adr_i:instd_logic_vector(31downto0); 248m3_sel_i:instd_logic_vector(3downto0); 249m3_we_i:instd_logic; 250m3_cyc_i:instd_logic;

A.4 Bus architecture 161

251m3_stb_i:instd_logic; 252m3_ack_o:outstd_logic; 253m3_err_o:outstd_logic; 254m3_rty_o:outstd_logic; 255m3_cab_i:instd_logic; 256 257--Master4 258m4_dat_i:instd_logic_vector(31downto0); 259m4_dat_o:outstd_logic_vector(31downto0); 260m4_adr_i:instd_logic_vector(31downto0); 261m4_sel_i:instd_logic_vector(3downto0); 262m4_we_i:instd_logic; 263m4_cyc_i:instd_logic; 264m4_stb_i:instd_logic; 265m4_ack_o:outstd_logic; 266m4_err_o:outstd_logic; 267m4_rty_o:outstd_logic; 268m4_cab_i:instd_logic; 269 270--Master5 271m5_dat_i:instd_logic_vector(31downto0); 272m5_dat_o:outstd_logic_vector(31downto0); 273m5_adr_i:instd_logic_vector(31downto0); 274m5_sel_i:instd_logic_vector(3downto0); 275m5_we_i:instd_logic; 276m5_cyc_i:instd_logic; 277m5_stb_i:instd_logic; 278m5_ack_o:outstd_logic; 279m5_err_o:outstd_logic; 280m5_rty_o:outstd_logic; 281m5_cab_i:instd_logic; 282 283--Master6 284m6_dat_i:instd_logic_vector(31downto0); 285m6_dat_o:outstd_logic_vector(31downto0); 286m6_adr_i:instd_logic_vector(31downto0);

162 HDL files

287m6_sel_i:instd_logic_vector(3downto0); 288m6_we_i:instd_logic; 289m6_cyc_i:instd_logic; 290m6_stb_i:instd_logic; 291m6_ack_o:outstd_logic; 292m6_err_o:outstd_logic; 293m6_rty_o:outstd_logic; 294m6_cab_i:instd_logic; 295 296--Master7 297m7_dat_i:instd_logic_vector(31downto0); 298m7_dat_o:outstd_logic_vector(31downto0); 299m7_adr_i:instd_logic_vector(31downto0); 300m7_sel_i:instd_logic_vector(3downto0); 301m7_we_i:instd_logic; 302m7_cyc_i:instd_logic; 303m7_stb_i:instd_logic; 304m7_ack_o:outstd_logic; 305m7_err_o:outstd_logic; 306m7_rty_o:outstd_logic; 307m7_cab_i:instd_logic; 308 309--Slave0 310s0_dat_i:instd_logic_vector(31downto0); 311s0_dat_o:outstd_logic_vector(31downto0); 312s0_adr_o:outstd_logic_vector(31downto0); 313s0_sel_o:outstd_logic_vector(3downto0); 314s0_we_o:outstd_logic; 315s0_cyc_o:outstd_logic; 316s0_stb_o:outstd_logic; 317s0_ack_i:instd_logic; 318s0_err_i:instd_logic; 319s0_rty_i:instd_logic; 320s0_cab_o:outstd_logic; 321 322--Slave1

A.4 Bus architecture 163

323s1_dat_i:instd_logic_vector(31downto0); 324s1_dat_o:outstd_logic_vector(31downto0); 325s1_adr_o:outstd_logic_vector(31downto0); 326s1_sel_o:outstd_logic_vector(3downto0); 327s1_we_o:outstd_logic; 328s1_cyc_o:outstd_logic; 329s1_stb_o:outstd_logic; 330s1_ack_i:instd_logic; 331s1_err_i:instd_logic; 332s1_rty_i:instd_logic; 333s1_cab_o:outstd_logic; 334 335--Slave2 336s2_dat_i:instd_logic_vector(31downto0); 337s2_dat_o:outstd_logic_vector(31downto0); 338s2_adr_o:outstd_logic_vector(31downto0); 339s2_sel_o:outstd_logic_vector(3downto0); 340s2_we_o:outstd_logic; 341s2_cyc_o:outstd_logic; 342s2_stb_o:outstd_logic; 343s2_ack_i:instd_logic; 344s2_err_i:instd_logic; 345s2_rty_i:instd_logic; 346s2_cab_o:outstd_logic; 347 348--Slave3 349s3_dat_i:instd_logic_vector(31downto0); 350s3_dat_o:outstd_logic_vector(31downto0); 351s3_adr_o:outstd_logic_vector(31downto0); 352s3_sel_o:outstd_logic_vector(3downto0); 353s3_we_o:outstd_logic; 354s3_cyc_o:outstd_logic; 355s3_stb_o:outstd_logic; 356s3_ack_i:instd_logic; 357s3_err_i:instd_logic; 358s3_rty_i:instd_logic;

164 HDL files

359s3_cab_o:outstd_logic; 360 361--Slave4 362s4_dat_i:instd_logic_vector(31downto0); 363s4_dat_o:outstd_logic_vector(31downto0); 364s4_adr_o:outstd_logic_vector(31downto0); 365s4_sel_o:outstd_logic_vector(3downto0); 366s4_we_o:outstd_logic; 367s4_cyc_o:outstd_logic; 368s4_stb_o:outstd_logic; 369s4_ack_i:instd_logic; 370s4_err_i:instd_logic; 371s4_rty_i:instd_logic; 372s4_cab_o:outstd_logic; 373 374--Slave5 375s5_dat_i:instd_logic_vector(31downto0); 376s5_dat_o:outstd_logic_vector(31downto0); 377s5_adr_o:outstd_logic_vector(31downto0); 378s5_sel_o:outstd_logic_vector(3downto0); 379s5_we_o:outstd_logic; 380s5_cyc_o:outstd_logic; 381s5_stb_o:outstd_logic; 382s5_ack_i:instd_logic; 383s5_err_i:instd_logic; 384s5_rty_i:instd_logic; 385s5_cab_o:outstd_logic; 386 387--Slave6 388s6_dat_i:instd_logic_vector(31downto0); 389s6_dat_o:outstd_logic_vector(31downto0); 390s6_adr_o:outstd_logic_vector(31downto0); 391s6_sel_o:outstd_logic_vector(3downto0); 392s6_we_o:outstd_logic; 393s6_cyc_o:outstd_logic; 394s6_stb_o:outstd_logic;

A.4 Bus architecture 165

395s6_ack_i:instd_logic; 396s6_err_i:instd_logic; 397s6_rty_i:instd_logic; 398s6_cab_o:outstd_logic; 399 400--Slave7 401s7_dat_i:instd_logic_vector(31downto0); 402s7_dat_o:outstd_logic_vector(31downto0); 403s7_adr_o:outstd_logic_vector(31downto0); 404s7_sel_o:outstd_logic_vector(3downto0); 405s7_we_o:outstd_logic; 406s7_cyc_o:outstd_logic; 407s7_stb_o:outstd_logic; 408s7_ack_i:instd_logic; 409s7_err_i:instd_logic; 410s7_rty_i:instd_logic; 411s7_cab_o:outstd_logic 412); 413endcomponent; 414 415------------------------------------------------------------------- 416-- 417--ICONcorecomponentdeclaration 418-- 419------------------------------------------------------------------- 420componenticon 421port 422( 423control0:outstd_logic_vector(35downto0); 424control1:outstd_logic_vector(35downto0) 425); 426endcomponent; 427 428------------------------------------------------------------------- 429-- 430--ILAcorecomponentdeclaration

166 HDL files

431-- 432------------------------------------------------------------------- 433componentila 434port 435( 436control:instd_logic_vector(35downto0); 437clk:instd_logic; 438data:instd_logic_vector(97downto0); 439trig0:instd_logic_vector(31downto0) 440); 441endcomponent; 442 443 444------------------------------------------------------------------- 445-- 446--VIOcorecomponentdeclaration 447-- 448------------------------------------------------------------------- 449componentvio 450port 451( 452control:instd_logic_vector(35downto0); 453async_out:outstd_logic_vector(7downto0) 454); 455endcomponent; 456 457componentBUFG 458port( 459O:outSTD_ULOGIC; 460I:inSTD_ULOGIC); 461endcomponent; 462 463componentIBUFG 464port( 465O:outSTD_ULOGIC; 466I:inSTD_ULOGIC);

A.4 Bus architecture 167

467endcomponent; 468 469 470 471-- 472--SIGNALS 473-- 474 475--Clocksignals 476--SIGNALclk:bit_t; 477SIGNALclk_div:bit_t; 478SIGNALclk_12_5MHZ:bit_t; 479SIGNALclkcount:unsigned(31downto0):="00000000000000000000000000000000"; 480 481 482SIGNALreset:bit_t; 483SIGNALreset_inv:bit_t; 484SIGNALpic_ints:std_logic_vector(19downto0); 485SIGNALclmode:std_logic_vector(1downto0); 486 487--Instructionsignals 488--SIGNALiwb_ack:bit_t; 489--SIGNALiwb_err:bit_t; 490--SIGNALiwb_rty:bit_t; 491--SIGNALiwb_dat_master:word_t; 492--SIGNALiwb_cyc:bit_t; 493--SIGNALiwb_adr:word_t; 494--SIGNALiwb_stb:bit_t; 495--SIGNALiwb_we:bit_t; 496--SIGNALiwb_sel:std_logic_vector(3downto0); 497--SIGNALiwb_dat_slave:word_t; 498--SIGNALiwb_cab:bit_t; 499 500--Datasignals 501--SIGNALdwb_ack:bit_t; 502--SIGNALdwb_ack_mem:bit_t;

168 HDL files

503--SIGNALdwb_ack_uart:bit_t; 504--SIGNALdwb_err:bit_t; 505--SIGNALdwb_rty:bit_t; 506--SIGNALdwb_dat_master:word_t; 507--SIGNALdwb_cyc:bit_t; 508--SIGNALdwb_adr:word_t; 509--SIGNALdwb_stb:bit_t; 510--SIGNALdwb_stb_mem:bit_t; 511--SIGNALdwb_stb_uart:bit_t; 512--SIGNALdwb_we:bit_t; 513--SIGNALdwb_sel:std_logic_vector(3downto0); 514--SIGNALdwb_dat_mem:word_t; 515--SIGNALdwb_dat_uart:word_t; 516--SIGNALdwb_dat_slave:word_t; 517--SIGNALdwb_cab:bit_t; 518 519--Master0Interface 520SIGNALm0_dat_i,m0_dat_o,m0_adr_o:word_t; 521SIGNALm0_sel_o:std_logic_vector(3downto0); 522SIGNALm0_we_o,m0_cyc_o,m0_stb_o,m0_ack_i,m0_err_i,m0_rty_i,m0_cab_o:bit_t; 523 524--Master1Interface 525SIGNALm1_dat_i,m1_dat_o,m1_adr_o:word_t; 526SIGNALm1_sel_o:std_logic_vector(3downto0); 527SIGNALm1_we_o,m1_cyc_o,m1_stb_o,m1_ack_i,m1_err_i,m1_rty_i,m1_cab_o:bit_t; 528 529--Master2Interface 530SIGNALm2_dat_i,m2_dat_o,m2_adr_o:word_t; 531SIGNALm2_sel_o:std_logic_vector(3downto0); 532SIGNALm2_we_o,m2_cyc_o,m2_stb_o,m2_ack_i,m2_err_i,m2_rty_i,m2_cab_o:bit_t; 533 534--Master3Interface 535SIGNALm3_dat_i,m3_dat_o,m3_adr_o:word_t; 536SIGNALm3_sel_o:std_logic_vector(3downto0); 537SIGNALm3_we_o,m3_cyc_o,m3_stb_o,m3_ack_i,m3_err_i,m3_rty_i,m3_cab_o:bit_t; 538

A.4 Bus architecture 169

539--Master4Interface 540SIGNALm4_dat_i,m4_dat_o,m4_adr_o:word_t; 541SIGNALm4_sel_o:std_logic_vector(3downto0); 542SIGNALm4_we_o,m4_cyc_o,m4_stb_o,m4_ack_i,m4_err_i,m4_rty_i,m4_cab_o:bit_t; 543 544--Master5Interface 545SIGNALm5_dat_i,m5_dat_o,m5_adr_o:word_t; 546SIGNALm5_sel_o:std_logic_vector(3downto0); 547SIGNALm5_we_o,m5_cyc_o,m5_stb_o,m5_ack_i,m5_err_i,m5_rty_i,m5_cab_o:bit_t; 548 549--Master6Interface 550SIGNALm6_dat_i,m6_dat_o,m6_adr_o:word_t; 551SIGNALm6_sel_o:std_logic_vector(3downto0); 552SIGNALm6_we_o,m6_cyc_o,m6_stb_o,m6_ack_i,m6_err_i,m6_rty_i,m6_cab_o:bit_t; 553 554--Master7Interface 555SIGNALm7_dat_i,m7_dat_o,m7_adr_o:word_t; 556SIGNALm7_sel_o:std_logic_vector(3downto0); 557SIGNALm7_we_o,m7_cyc_o,m7_stb_o,m7_ack_i,m7_err_i,m7_rty_i,m7_cab_o:bit_t; 558 559--Slaver0Interface 560SIGNALs0_dat_i,s0_dat_o,s0_adr_i:word_t; 561SIGNALs0_sel_i:std_logic_vector(3downto0); 562SIGNALs0_we_i,s0_cyc_i,s0_stb_i,s0_ack_o,s0_err_o,s0_rty_o,s0_cab_i:bit_t; 563 564--Slaver1Interface 565SIGNALs1_dat_i,s1_dat_o,s1_adr_i:word_t; 566SIGNALs1_sel_i:std_logic_vector(3downto0); 567SIGNALs1_we_i,s1_cyc_i,s1_stb_i,s1_ack_o,s1_err_o,s1_rty_o,s1_cab_i:bit_t; 568 569--Slaver2Interface 570SIGNALs2_dat_i,s2_dat_o,s2_adr_i:word_t; 571SIGNALs2_sel_i:std_logic_vector(3downto0); 572SIGNALs2_we_i,s2_cyc_i,s2_stb_i,s2_ack_o,s2_err_o,s2_rty_o,s2_cab_i:bit_t; 573 574--Slaver3Interface

170 HDL files

575SIGNALs3_dat_i,s3_dat_o,s3_adr_i:word_t; 576SIGNALs3_sel_i:std_logic_vector(3downto0); 577SIGNALs3_we_i,s3_cyc_i,s3_stb_i,s3_ack_o,s3_err_o,s3_rty_o,s3_cab_i:bit_t; 578 579--Slaver4Interface 580SIGNALs4_dat_i,s4_dat_o,s4_adr_i:word_t; 581SIGNALs4_sel_i:std_logic_vector(3downto0); 582SIGNALs4_we_i,s4_cyc_i,s4_stb_i,s4_ack_o,s4_err_o,s4_rty_o,s4_cab_i:bit_t; 583 584--Slaver5Interface 585SIGNALs5_dat_i,s5_dat_o,s5_adr_i:word_t; 586SIGNALs5_sel_i:std_logic_vector(3downto0); 587SIGNALs5_we_i,s5_cyc_i,s5_stb_i,s5_ack_o,s5_err_o,s5_rty_o,s5_cab_i:bit_t; 588 589--Slaver6Interface 590SIGNALs6_dat_i,s6_dat_o,s6_adr_i:word_t; 591SIGNALs6_sel_i:std_logic_vector(3downto0); 592SIGNALs6_we_i,s6_cyc_i,s6_stb_i,s6_ack_o,s6_err_o,s6_rty_o,s6_cab_i:bit_t; 593 594--Slaver7Interface 595SIGNALs7_dat_i,s7_dat_o,s7_adr_i:word_t; 596SIGNALs7_sel_i:std_logic_vector(3downto0); 597SIGNALs7_we_i,s7_cyc_i,s7_stb_i,s7_ack_o,s7_err_o,s7_rty_o,s7_cab_i:bit_t; 598 599--acksignals 600SIGNALack0:bit_t; 601SIGNALack1:bit_t; 602SIGNALack2:bit_t; 603SIGNALack3:bit_t; 604SIGNALack4:bit_t; 605SIGNALack5:bit_t; 606SIGNALack6:bit_t; 607SIGNALack7:bit_t; 608 609 610

A.4 Bus architecture 171

611--Zerosignals 612SIGNALzero:bit_t; 613SIGNALzero32:word_t; 614 615--Serialsignal 616SIGNALtx_pad:bit_t; 617 618------------------------------------------------------------------- 619-- 620--ILAcoresignaldeclarations 621-- 622------------------------------------------------------------------- 623signalcontrol0:std_logic_vector(35downto0); 624signalclk:std_logic; 625signaldata:std_logic_vector(97downto0); 626signaltrig0:std_logic_vector(31downto0); 627 628------------------------------------------------------------------- 629-- 630--VIOcoresignaldeclarations 631-- 632------------------------------------------------------------------- 633signalcontrol1:std_logic_vector(35downto0); 634signalasync_out:std_logic_vector(7downto0); 635 636------------------------------------------------------------------- 637-- 638--ICONcoresignaldeclarations 639-- 640------------------------------------------------------------------- 641--signalcontrol0:std_logic_vector(35downto0); 642--signalcontrol1:std_logic_vector(35downto0); 643 644 645begin 646Clock_buf:BUFG

172 HDL files

647portmap(O=>clk_12_5MHZ, 648I=>clk_div); 649 650rst_buf:IBUFG 651portmap(O=>reset, 652I=>rst_i); 653 654process(clk_i) 655begin 656ifclk_i’eventandclk_i=’1’then 657clkcount<=clkcount+1; 658endif; 659endprocess; 660 661clk_div<=conv_std_logic_vector(clkcount,3)(2); 662running<=conv_std_logic_vector(clkcount,24)(23)andreset; 663 664zero32<="00000000000000000000000000000000"; 665zero<=’0’; 666pic_ints<="00000000000000000000"; 667clmode<="00";--SameclockforWISHBONEandCPU 668 669reset_inv<=notreset; 670 671 672CPU0:or1200_top 673PORTMAP( 674clk_i=>clk_12_5MHZ, 675rst_i=>reset_inv, 676pic_ints_i=>pic_ints, 677clmode_i=>clmode, 678 679--InstructionWISHBONEinterface 680iwb_clk_i=>clk_12_5MHZ, 681iwb_rst_i=>reset_inv, 682iwb_ack_i=>ack0,

A.4 Bus architecture 173

683iwb_err_i=>m0_err_i, 684iwb_rty_i=>m0_rty_i, 685iwb_dat_i=>m0_dat_i, 686iwb_cyc_o=>m0_cyc_o, 687iwb_adr_o=>m0_adr_o, 688iwb_stb_o=>m0_stb_o, 689iwb_we_o=>m0_we_o, 690iwb_sel_o=>m0_sel_o, 691iwb_dat_o=>m0_dat_o, 692iwb_cab_o=>m0_cab_o, 693 694--DataWISHBONEinterface 695dwb_clk_i=>clk_12_5MHZ, 696dwb_rst_i=>reset_inv, 697dwb_ack_i=>ack1, 698dwb_err_i=>m1_err_i, 699dwb_rty_i=>m1_rty_i, 700dwb_dat_i=>m1_dat_i, 701dwb_cyc_o=>m1_cyc_o, 702dwb_adr_o=>m1_adr_o, 703dwb_stb_o=>m1_stb_o, 704dwb_we_o=>m1_we_o, 705dwb_sel_o=>m1_sel_o, 706dwb_dat_o=>m1_dat_o, 707dwb_cab_o=>m1_cab_o, 708 709--Debuginterface 710dbg_stall_i=>zero, 711dbg_ewt_i=>zero, 712dbg_lss_o=>open, 713dbg_is_o=>open, 714dbg_wp_o=>open, 715dbg_bp_o=>open, 716dbg_stb_i=>zero, 717dbg_we_i=>zero, 718dbg_adr_i=>zero32,

174 HDL files

719dbg_dat_i=>zero32, 720dbg_dat_o=>open, 721dbg_ack_o=>open, 722 723--PowerManagementinterface 724pm_cpustall_i=>zero, 725pm_clksd_o=>open, 726pm_dc_gate_o=>open, 727pm_ic_gate_o=>open, 728pm_dmmu_gate_o=>open, 729pm_immu_gate_o=>open, 730pm_tt_gate_o=>open, 731pm_cpu_gate_o=>open, 732pm_wakeup_o=>open, 733pm_lvolt_o=>open 734); 735 736CPU1:or1200_top 737PORTMAP( 738clk_i=>clk_12_5MHZ, 739rst_i=>reset_inv, 740pic_ints_i=>pic_ints, 741clmode_i=>clmode, 742 743--InstructionWISHBONEinterface 744iwb_clk_i=>clk_12_5MHZ, 745iwb_rst_i=>reset_inv, 746iwb_ack_i=>ack2, 747iwb_err_i=>m2_err_i, 748iwb_rty_i=>m2_rty_i, 749iwb_dat_i=>m2_dat_i, 750iwb_cyc_o=>m2_cyc_o, 751iwb_adr_o=>m2_adr_o, 752iwb_stb_o=>m2_stb_o, 753iwb_we_o=>m2_we_o, 754iwb_sel_o=>m2_sel_o,

A.4 Bus architecture 175

755iwb_dat_o=>m2_dat_o, 756iwb_cab_o=>m2_cab_o, 757 758--DataWISHBONEinterface 759dwb_clk_i=>clk_12_5MHZ, 760dwb_rst_i=>reset_inv, 761dwb_ack_i=>ack3, 762dwb_err_i=>m3_err_i, 763dwb_rty_i=>m3_rty_i, 764dwb_dat_i=>m3_dat_i, 765dwb_cyc_o=>m3_cyc_o, 766dwb_adr_o=>m3_adr_o, 767dwb_stb_o=>m3_stb_o, 768dwb_we_o=>m3_we_o, 769dwb_sel_o=>m3_sel_o, 770dwb_dat_o=>m3_dat_o, 771dwb_cab_o=>m3_cab_o, 772 773--Debuginterface 774dbg_stall_i=>zero, 775dbg_ewt_i=>zero, 776dbg_lss_o=>open, 777dbg_is_o=>open, 778dbg_wp_o=>open, 779dbg_bp_o=>open, 780dbg_stb_i=>zero, 781dbg_we_i=>zero, 782dbg_adr_i=>zero32, 783dbg_dat_i=>zero32, 784dbg_dat_o=>open, 785dbg_ack_o=>open, 786 787--PowerManagementinterface 788pm_cpustall_i=>zero, 789pm_clksd_o=>open, 790pm_dc_gate_o=>open,

176 HDL files

791pm_ic_gate_o=>open, 792pm_dmmu_gate_o=>open, 793pm_immu_gate_o=>open, 794pm_tt_gate_o=>open, 795pm_cpu_gate_o=>open, 796pm_wakeup_o=>open, 797pm_lvolt_o=>open 798); 799 800CPU2:or1200_top 801PORTMAP( 802clk_i=>clk_12_5MHZ, 803rst_i=>reset_inv, 804pic_ints_i=>pic_ints, 805clmode_i=>clmode, 806 807--InstructionWISHBONEinterface 808iwb_clk_i=>clk_12_5MHZ, 809iwb_rst_i=>reset_inv, 810iwb_ack_i=>ack4, 811iwb_err_i=>m4_err_i, 812iwb_rty_i=>m4_rty_i, 813iwb_dat_i=>m4_dat_i, 814iwb_cyc_o=>m4_cyc_o, 815iwb_adr_o=>m4_adr_o, 816iwb_stb_o=>m4_stb_o, 817iwb_we_o=>m4_we_o, 818iwb_sel_o=>m4_sel_o, 819iwb_dat_o=>m4_dat_o, 820iwb_cab_o=>m4_cab_o, 821 822--DataWISHBONEinterface 823dwb_clk_i=>clk_12_5MHZ, 824dwb_rst_i=>reset_inv, 825dwb_ack_i=>ack5, 826dwb_err_i=>m5_err_i,

A.4 Bus architecture 177

827dwb_rty_i=>m5_rty_i, 828dwb_dat_i=>m5_dat_i, 829dwb_cyc_o=>m5_cyc_o, 830dwb_adr_o=>m5_adr_o, 831dwb_stb_o=>m5_stb_o, 832dwb_we_o=>m5_we_o, 833dwb_sel_o=>m5_sel_o, 834dwb_dat_o=>m5_dat_o, 835dwb_cab_o=>m5_cab_o, 836 837--Debuginterface 838dbg_stall_i=>zero, 839dbg_ewt_i=>zero, 840dbg_lss_o=>open, 841dbg_is_o=>open, 842dbg_wp_o=>open, 843dbg_bp_o=>open, 844dbg_stb_i=>zero, 845dbg_we_i=>zero, 846dbg_adr_i=>zero32, 847dbg_dat_i=>zero32, 848dbg_dat_o=>open, 849dbg_ack_o=>open, 850 851--PowerManagementinterface 852pm_cpustall_i=>zero, 853pm_clksd_o=>open, 854pm_dc_gate_o=>open, 855pm_ic_gate_o=>open, 856pm_dmmu_gate_o=>open, 857pm_immu_gate_o=>open, 858pm_tt_gate_o=>open, 859pm_cpu_gate_o=>open, 860pm_wakeup_o=>open, 861pm_lvolt_o=>open 862);

178 HDL files

863 864--CPU3:or1200_top 865--PORTMAP( 866--clk_i=>clk_12_5MHZ, 867--rst_i=>reset_inv, 868--pic_ints_i=>pic_ints, 869--clmode_i=>clmode, 870-- 871----InstructionWISHBONEinterface 872--iwb_clk_i=>clk_12_5MHZ, 873--iwb_rst_i=>reset_inv, 874--iwb_ack_i=>ack6, 875--iwb_err_i=>m6_err_i, 876--iwb_rty_i=>m6_rty_i, 877--iwb_dat_i=>m6_dat_i, 878--iwb_cyc_o=>m6_cyc_o, 879--iwb_adr_o=>m6_adr_o, 880--iwb_stb_o=>m6_stb_o, 881--iwb_we_o=>m6_we_o, 882--iwb_sel_o=>m6_sel_o, 883--iwb_dat_o=>m6_dat_o, 884--iwb_cab_o=>m6_cab_o, 885-- 886----DataWISHBONEinterface 887--dwb_clk_i=>clk_12_5MHZ, 888--dwb_rst_i=>reset_inv, 889--dwb_ack_i=>ack7, 890--dwb_err_i=>m7_err_i, 891--dwb_rty_i=>m7_rty_i, 892--dwb_dat_i=>m7_dat_i, 893--dwb_cyc_o=>m7_cyc_o, 894--dwb_adr_o=>m7_adr_o, 895--dwb_stb_o=>m7_stb_o, 896--dwb_we_o=>m7_we_o, 897--dwb_sel_o=>m7_sel_o, 898--dwb_dat_o=>m7_dat_o,

A.4 Bus architecture 179

899--dwb_cab_o=>m7_cab_o, 900-- 901----Debuginterface 902--dbg_stall_i=>zero, 903--dbg_ewt_i=>zero, 904--dbg_lss_o=>open, 905--dbg_is_o=>open, 906--dbg_wp_o=>open, 907--dbg_bp_o=>open, 908--dbg_stb_i=>zero, 909--dbg_we_i=>zero, 910--dbg_adr_i=>zero32, 911--dbg_dat_i=>zero32, 912--dbg_dat_o=>open, 913--dbg_ack_o=>open, 914-- 915----PowerManagementinterface 916--pm_cpustall_i=>zero, 917--pm_clksd_o=>open, 918--pm_dc_gate_o=>open, 919--pm_ic_gate_o=>open, 920--pm_dmmu_gate_o=>open, 921--pm_immu_gate_o=>open, 922--pm_tt_gate_o=>open, 923--pm_cpu_gate_o=>open, 924--pm_wakeup_o=>open, 925--pm_lvolt_o=>open 926--); 927 928imem:core_mem 929portmap( 930--I/Oports 931wb_clk_i=>clk_12_5MHZ, 932wb_rst_i=>reset, 933 934--WBslavei/f

180 HDL files

935wb_data_i=>s0_dat_i, 936wb_data_o=>s0_dat_o, 937wb_adr_i=>s0_adr_i, 938wb_sel_i=>s0_sel_i, 939wb_we_i=>s0_we_i, 940wb_cyc_i=>s0_cyc_i, 941wb_stb_i=>s0_stb_i, 942wb_ack_o=>s0_ack_o, 943wb_err_o=>s0_err_o 944); 945 946 947dmem:core_mem 948portmap( 949--I/Oports 950wb_clk_i=>clk_12_5MHZ, 951wb_rst_i=>reset, 952 953--WBslavei/f 954wb_data_i=>s1_dat_i, 955wb_data_o=>s1_dat_o, 956wb_adr_i=>s1_adr_i, 957wb_sel_i=>s1_sel_i, 958wb_we_i=>s1_we_i, 959wb_cyc_i=>s1_cyc_i, 960wb_stb_i=>s1_stb_i, 961wb_ack_o=>s1_ack_o, 962wb_err_o=>s1_err_o 963); 964 965sema:semaphore 966portmap( 967--I/Oports 968wb_clk_i=>clk_12_5MHZ, 969wb_rst_i=>reset, 970

A.4 Bus architecture 181

971--WBslavei/f 972wb_data_i=>s3_dat_i, 973wb_data_o=>s3_dat_o, 974wb_adr_i=>s3_adr_i, 975wb_sel_i=>s3_sel_i, 976wb_we_i=>s3_we_i, 977wb_cyc_i=>s3_cyc_i, 978wb_stb_i=>s3_stb_i, 979wb_ack_o=>s3_ack_o, 980wb_err_o=>s3_err_o 981); 982 983 984uart:uart_top 985portmap( 986--I/OPorts 987wb_clk_i=>clk_12_5MHZ, 988wb_rst_i=>reset_inv, 989 990--WBslavei/f 991wb_adr_i=>s2_adr_i(4downto0), 992wb_dat_i=>s2_dat_i, 993wb_dat_o=>s2_dat_o, 994wb_we_i=>s2_we_i, 995wb_stb_i=>s2_stb_i, 996wb_cyc_i=>s2_cyc_i, 997wb_ack_o=>s2_ack_o, 998wb_sel_i=>s2_sel_i, 999 1000--UARTsignals 1001 1002int_o=>open, 1003 1004--serialinput/output 1005stx_pad_o=>tx_pad, 1006srx_pad_i=>rx,

182 HDL files

1007 1008--modemsignals 1009rts_pad_o=>open, 1010cts_pad_i=>’1’, 1011dtr_pad_o=>open, 1012dsr_pad_i=>’1’, 1013ri_pad_i=>’1’, 1014dcd_pad_i=>’1’ 1015 1016); 1017 1018 1019conbus:wb_conbus_top 1020portmap( 1021 1022--I/Oports 1023clk_i=>clk_12_5MHZ, 1024rst_i=>reset_inv,--activehigh 1025 1026--Master0 1027m0_dat_i=>m0_dat_o, 1028m0_dat_o=>m0_dat_i, 1029m0_adr_i=>m0_adr_o, 1030m0_sel_i=>m0_sel_o, 1031m0_we_i=>m0_we_o, 1032m0_cyc_i=>m0_cyc_o, 1033m0_stb_i=>m0_stb_o, 1034m0_ack_o=>m0_ack_i, 1035m0_err_o=>open,--m0_err_i, 1036m0_rty_o=>open,--m0_rty_i, 1037m0_cab_i=>m0_cab_o, 1038 1039--Master1 1040m1_dat_i=>m1_dat_o, 1041m1_dat_o=>m1_dat_i, 1042m1_adr_i=>m1_adr_o,

A.4 Bus architecture 183

1043m1_sel_i=>m1_sel_o, 1044m1_we_i=>m1_we_o, 1045m1_cyc_i=>m1_cyc_o, 1046m1_stb_i=>m1_stb_o, 1047m1_ack_o=>m1_ack_i, 1048m1_err_o=>open,--m1_err_i, 1049m1_rty_o=>open,--m1_rty_i, 1050m1_cab_i=>m1_cab_o, 1051 1052--Master2 1053m2_dat_i=>m2_dat_o, 1054m2_dat_o=>m2_dat_i, 1055m2_adr_i=>m2_adr_o, 1056m2_sel_i=>m2_sel_o, 1057m2_we_i=>m2_we_o, 1058m2_cyc_i=>m2_cyc_o, 1059m2_stb_i=>m2_stb_o, 1060m2_ack_o=>m2_ack_i, 1061m2_err_o=>open,--m2_err_i, 1062m2_rty_o=>open,--m2_rty_i, 1063m2_cab_i=>m2_cab_o, 1064 1065--Master3 1066m3_dat_i=>m3_dat_o, 1067m3_dat_o=>m3_dat_i, 1068m3_adr_i=>m3_adr_o, 1069m3_sel_i=>m3_sel_o, 1070m3_we_i=>m3_we_o, 1071m3_cyc_i=>m3_cyc_o, 1072m3_stb_i=>m3_stb_o, 1073m3_ack_o=>m3_ack_i, 1074m3_err_o=>open,--m3_err_i, 1075m3_rty_o=>open,--m3_rty_i, 1076m3_cab_i=>m3_cab_o, 1077 1078--Master4

184 HDL files

1079m4_dat_i=>m4_dat_o, 1080m4_dat_o=>m4_dat_i, 1081m4_adr_i=>m4_adr_o, 1082m4_sel_i=>m4_sel_o, 1083m4_we_i=>m4_we_o, 1084m4_cyc_i=>m4_cyc_o, 1085m4_stb_i=>m4_stb_o, 1086m4_ack_o=>m4_ack_i, 1087m4_err_o=>open,--m4_err_i, 1088m4_rty_o=>open,--m4_rty_i, 1089m4_cab_i=>m4_cab_o, 1090 1091--Master5 1092m5_dat_i=>m5_dat_o, 1093m5_dat_o=>m5_dat_i, 1094m5_adr_i=>m5_adr_o, 1095m5_sel_i=>m5_sel_o, 1096m5_we_i=>m5_we_o, 1097m5_cyc_i=>m5_cyc_o, 1098m5_stb_i=>m5_stb_o, 1099m5_ack_o=>m5_ack_i, 1100m5_err_o=>open,--m5_err_i, 1101m5_rty_o=>open,--m5_rty_i, 1102m5_cab_i=>m5_cab_o, 1103 1104--Master6 1105m6_dat_i=>m6_dat_o, 1106m6_dat_o=>m6_dat_i, 1107m6_adr_i=>m6_adr_o, 1108m6_sel_i=>m6_sel_o, 1109m6_we_i=>m6_we_o, 1110m6_cyc_i=>m6_cyc_o, 1111m6_stb_i=>m6_stb_o, 1112m6_ack_o=>m6_ack_i, 1113m6_err_o=>open,--m6_err_i, 1114m6_rty_o=>open,--m6_rty_i,

A.4 Bus architecture 185

1115m6_cab_i=>m6_cab_o, 1116 1117--Master7 1118m7_dat_i=>m7_dat_o, 1119m7_dat_o=>m7_dat_i, 1120m7_adr_i=>m7_adr_o, 1121m7_sel_i=>m7_sel_o, 1122m7_we_i=>m7_we_o, 1123m7_cyc_i=>m7_cyc_o, 1124m7_stb_i=>m7_stb_o, 1125m7_ack_o=>m7_ack_i, 1126m7_err_o=>open,--m7_err_i, 1127m7_rty_o=>open,--m7_rty_i, 1128m7_cab_i=>m7_cab_o, 1129 1130--Slave0 1131s0_dat_i=>s0_dat_o, 1132s0_dat_o=>s0_dat_i, 1133s0_adr_o=>s0_adr_i, 1134s0_sel_o=>s0_sel_i, 1135s0_we_o=>s0_we_i, 1136s0_cyc_o=>s0_cyc_i, 1137s0_stb_o=>s0_stb_i, 1138s0_ack_i=>s0_ack_o, 1139s0_err_i=>s0_err_o, 1140s0_rty_i=>s0_rty_o, 1141s0_cab_o=>s0_cab_i, 1142 1143--Slave1 1144s1_dat_i=>s1_dat_o, 1145s1_dat_o=>s1_dat_i, 1146s1_adr_o=>s1_adr_i, 1147s1_sel_o=>s1_sel_i, 1148s1_we_o=>s1_we_i, 1149s1_cyc_o=>s1_cyc_i, 1150s1_stb_o=>s1_stb_i,

186 HDL files

1151s1_ack_i=>s1_ack_o, 1152s1_err_i=>s1_err_o, 1153s1_rty_i=>s1_rty_o, 1154s1_cab_o=>s1_cab_i, 1155 1156--Slave2 1157s2_dat_i=>s2_dat_o, 1158s2_dat_o=>s2_dat_i, 1159s2_adr_o=>s2_adr_i, 1160s2_sel_o=>s2_sel_i, 1161s2_we_o=>s2_we_i, 1162s2_cyc_o=>s2_cyc_i, 1163s2_stb_o=>s2_stb_i, 1164s2_ack_i=>s2_ack_o, 1165s2_err_i=>s2_err_o, 1166s2_rty_i=>s2_rty_o, 1167s2_cab_o=>s2_cab_i, 1168 1169--Slave3 1170s3_dat_i=>s3_dat_o, 1171s3_dat_o=>s3_dat_i, 1172s3_adr_o=>s3_adr_i, 1173s3_sel_o=>s3_sel_i, 1174s3_we_o=>s3_we_i, 1175s3_cyc_o=>s3_cyc_i, 1176s3_stb_o=>s3_stb_i, 1177s3_ack_i=>s3_ack_o, 1178s3_err_i=>s3_err_o, 1179s3_rty_i=>s3_rty_o, 1180s3_cab_o=>s3_cab_i, 1181 1182--Slave4 1183s4_dat_i=>s4_dat_o, 1184s4_dat_o=>s4_dat_i, 1185s4_adr_o=>s4_adr_i, 1186s4_sel_o=>s4_sel_i,

A.4 Bus architecture 187

1187s4_we_o=>s4_we_i, 1188s4_cyc_o=>s4_cyc_i, 1189s4_stb_o=>s4_stb_i, 1190s4_ack_i=>s4_ack_o, 1191s4_err_i=>s4_err_o, 1192s4_rty_i=>s4_rty_o, 1193s4_cab_o=>s4_cab_i, 1194 1195--Slave5 1196s5_dat_i=>s5_dat_o, 1197s5_dat_o=>s5_dat_i, 1198s5_adr_o=>s5_adr_i, 1199s5_sel_o=>s5_sel_i, 1200s5_we_o=>s5_we_i, 1201s5_cyc_o=>s5_cyc_i, 1202s5_stb_o=>s5_stb_i, 1203s5_ack_i=>s5_ack_o, 1204s5_err_i=>s5_err_o, 1205s5_rty_i=>s5_rty_o, 1206s5_cab_o=>s5_cab_i, 1207 1208--Slave6 1209s6_dat_i=>s6_dat_o, 1210s6_dat_o=>s6_dat_i, 1211s6_adr_o=>s6_adr_i, 1212s6_sel_o=>s6_sel_i, 1213s6_we_o=>s6_we_i, 1214s6_cyc_o=>s6_cyc_i, 1215s6_stb_o=>s6_stb_i, 1216s6_ack_i=>s6_ack_o, 1217s6_err_i=>s6_err_o, 1218s6_rty_i=>s6_rty_o, 1219s6_cab_o=>s6_cab_i, 1220 1221--Slave7 1222s7_dat_i=>s7_dat_o,

In document Multiprocessor in a FPGA (Sider 163-200)